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HIP7030A2 Datasheet(PDF) 46 Page - Intersil Corporation |
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HIP7030A2 Datasheet(HTML) 46 Page - Intersil Corporation |
46 / 56 page 46 Alphabetical Listing The complete instruction set is given in alphabetical order in Table 16. Opcode Map Table 17 is an opcode map for the instructions used on the MCU. Addressing Modes The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the code to all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. Short indexed accesses are single byte instructions, while the longest instructions (three bytes) permit accessing tables throughout memory. Short absolute (direct) and long abso- lute (extended) addressing are also included. One and two byte direct addressing instructions access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory. Table 17 shows the addressing modes for each instruction, with the effects each instruction has on the condition code register. The term “effective address” (EA) is used in describing the various addressing modes, and is defined as the byte address to or from which the argument for an instruction is fetched or stored. The ten addressing modes of the proces- sor are described below. Parentheses are used to indicate “contents of” the location or register referred to; e.g., (PC) indicates the contents of the location pointed to by the PC. An arrow indicates “is replaced by”, and a colon indicates concatenation of two bytes. Inherent In inherent instructions, all the information necessary to exe- cute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, and no other arguments, are included in this mode. Immediate In immediate addressing, the operand is contained in the byte immediately following the opcode. Immediate address- ing is used to access constants which do not change during program execution (e.g., a constant used to initialize a loop counter). EA = PC + 1; PC ← PC + 2 Direct In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two byte instruction. This includes most on-chip RAM and all I/O registers. Direct addressing is efficient in both memory and time. EA = (PC +1); PC ← PC + 2 Address Bus High 0; Address Bus Low ← (PC + 1) Extended In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode. Instructions with extended addressing modes are capable of referencing arguments anywhere in memory with a single three-byte instruction. EA = (PC + 1) : (PC + 2); PC ← PC + 3 Address Bus High ← (PC + 1); Address Bus Low ← (PC + 2) Indexed, No Offset In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index regis- ter. Thus, this addressing mode can access the first 256 memory locations. These instructions are only one byte long. This mode is used to move a pointer through a table or to address a frequently referenced RAM or I/O location. EA = X; PC ← PC + 1 Address Bus High ← 0; Address Bus Low ← X Indexed, 8-Bit Offset Here the EA is obtained by adding the contents of the byte fol- lowing the opcode to that of the index register; therefore, the operand is located anywhere within the lowest 511 memory locations. For example, this mode of addressing is useful for selecting the mth element in a n element table. All instructions are two bytes. The content of the index register (S) is not changed. The content of (PC + 1) is an unsigned 8-bit integer. One byte offset indexing permits look-up tables to be easily accessed in either RAM or ROM. EA = X + (PC + 1); PC ← PC + 2 Address Bus High ← K; Address Bus Low ← X + (PC + 1) where: K = the carry from the addition of x + (PC + 1). Indexed, 16-Bit Offset In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This addressing mode can be used in a manner similar to indexed 8-bit offset, except that this three byte instruction allows tables to be anywhere in memory (e.g., jump tables in ROM). The content of the index register is not changed. EA = X + [(PC + 1) : (PC + 2)]; PC ← PC + 3 Address Bus High ← (PC + 1) + K Address Bus Low ← X + (PC + 2) where: K = The carry from the addition of X + (PC + 2). Relative Relative addressing is only used in branch instructions. In relative addressing, the content of the 8-bit signed byte fol- lowing the opcode (the offset) is added to the PC if and only if the branch condition is true. Otherwise, control proceeds to the next instruction. The span of relative addressing is lim- ited to the range of -126 to +129 bytes from the branch instruction opcode location. EA = PC + 2 + (PC + 1); PC ← EA if branch taken; otherwise, EA = PC ← PC + 2. HIP7030A2 |
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