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HIP6503CB Datasheet(PDF) 8 Page - Intersil Corporation |
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HIP6503CB Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 14 page 8 Not shown in these diagrams is the deglitching feature used to protect against false sleep state tripping. Both S3 and S5 pins are protected against noise by a 2 µs filter (typically 1 - 4 µs). This feature is useful in noisy computer environments if the control signals have to travel over significant distances. Additionally, the S3 pin features a 200 µs delay in transitioning to sleep states. Once the S3 pin goes low, an internal timer is activated. At the end of the 200 µs interval, if the S5 pin is low, the HIP6503 switches into S5 sleep state; if the S5 pin is high, the HIP6503 goes into S3 sleep state. Soft-Start Circuit SOFT-START INTO SLEEP STATES (S3, S4/S5) The 5VSB POR function initiates the soft-start sequence. An internal 10 µA current source charges an external capacitor. The error amplifiers reference inputs are clamped to a level proportional to the SS (soft-start) pin voltage. As the SS pin voltage slews from about 1.25V to 2.5V, the input clamp allows a rapid and controlled output voltage rise. Figure 7 shows the soft-start sequence for the typical application start-up in sleep state with all output voltages enabled. At time T0 5VSB (bias) is applied to the circuit. At time T1 the 5VSB surpasses POR level. An internal fast charge circuit quickly raises the SS capacitor voltage to approximately 1V, then the 10 µA current source continues the charging. The soft-start capacitor voltage reaches approximately 1.25V at time T2, at which point the 3.3VDUAL/3.3VSB and 1.8VSB error amplifiers’ reference inputs start their transition, resulting in the output voltages ramping up proportionally. The ramp-up continues until time T3 when the two voltages reach the set value. As the soft- start capacitor voltage reaches approximately 2.75V, the under-voltage monitoring circuit of this output is activated and the soft-start capacitor is quickly discharged to approximately 1.25V. Following the 3ms (typical) time-out between T3 and T4, the MSEL and EN5VDL selections are latched in, and the soft-start capacitor commences a second ramp-up designed to smoothly bring up the remainder of the voltages required by the system. At time T5 all voltages are within regulation limits, and as the SS voltage reaches 2.75V, all the remaining UV monitors are activated and the SS capacitor is quickly discharged to 1.25V, where it remains until the next transition. As the 2.5VCLK output is only active while in an active state, it does not come up, but FIGURE 5. 5VDUAL TIMING DIAGRAM FOR EN5VDL = 0; 3VDUAL/3VSB 5VSB 3.3V, S3 S5 5VDLSB DLA 3V3DLSB 3V3DL 5VDL 5V, 12V FIGURE 6. 2.5VMEM, 3.3VMEM, AND 2.5VCLK TIMING DIAGRAM 5VSB 3.3V, S3 S5 DRV2 VSEN 2 VSEN2 INTERNAL DEVICES VCLK DLA VSEN1 5V, 12V FIGURE 7. SOFT-START INTERVAL IN A SLEEP STATE (ALL OUTPUTS ENABLED) 0V 0V TIME SOFT-START (1V/DIV) OUTPUT (1V/DIV) VOLTAGES VOUT1 (1.8VSB) VOUT2 VOUT5 (5VDUAL) T1 T2 T3 T0 5VSB (1V/DIV) T5 T4 VOUT3 (3.3VDUAL/3.3VSB) (2.5VMEM) VOUT4 (2.5VCLK) HIP6503 |
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