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HIP6501EVAL1 Datasheet(PDF) 5 Page - Intersil Corporation |
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HIP6501EVAL1 Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 14 page 5 Functional Pin Description 5VSB (Pin 1) Provide a 5V bias supply for the IC to this pin by connecting it to the ATX 5VSB output. This pin also provides the base bias current for all the external NPN transistors controlled by the IC. The voltage at this pin is monitored for power-on reset (POR) purposes. GND (Pin 8) Signal ground for the IC. All voltage levels are measured with respect to this pin. S3 and S5 (Pins 6 and 7) These pins switch the IC’s operating state from active (S0, S1) to S3 and S4/S5 sleep states. Connect S3 to SLP_S3 and S5 to SLP_S5. These are digital inputs featuring internal 70k Ω (typical) resistor pull-ups to 5VSB. Internal circuitry de- glitches the S3 pin for disturbances. Additional circuitry blocks any illegal state transitions (such as S3 to S4/S5 or vice versa). When entering an S4/S5 sleep state, the S3 signal is allowed to go low as far as 200 µs (typically) ahead of the S5 signal. EN3VDL and EN5VDL (Pins 2 and 5) These pins control the logic governing the output behavior in response to S3 and S4/S5 requests. These are digital inputs whose status can only be changed during active states operation or during chip shutdown (SS pin grounded by external open-drain device). The input information is latched- in when entering a sleep state, as well as following 5VSB POR release or exit from shutdown. FAULT/MSEL (Pin 9) This is a multiplexed function pin allowing the setting of the memory output voltage to either 2.5V or 3.3V (for RDRAM or SDRAM memory systems). The memory voltage setting is latched-in 3ms (typically) after 5VSB POR release. In case of an under-voltage on any of the outputs or an over- temperature event, this pin is used to report the fault condition by being pulled to 5VSB. SS (Pin 13) Connect a small ceramic capacitor (allowable range: 5nF- 0.22 µF; 0.1µF recommended) from this pin to GND. The internal Soft-Start (SS) current source along with the external capacitor creates a voltage ramp used to control the ramp-up of the output voltages. Pulling this pin low with an open-drain device shuts down all the outputs as well as 5VDUAL SWITCH CONTROLLER (VOUT3) 5VDL Under-Voltage Rising Threshold - 3.750 - V 5VDL Under-Voltage Hysteresis - 260 - mV 5VDLSB Output Drive Current I5VDLSB 5VDLSB = 4V -20 - -40 mA 5VDLSB Pull-up Impedance to 5VSB - 350 - Ω TIMING INTERVALS Active State Assessment Past 12V Threshold Note 2 40 50 60 ms Maximum Allowable S3 to S5 Skew - 200 - µs 5VSB POR Extension Past Threshold Voltage - 3.3 - ms CONTROL I/O (S3, S5, EN3VDL, EN5VDL, FAULT) High Level Threshold - - 2.2 V Low Level Threshold 0.8 - - V S3,S5 Internal Pull-up Impedance to 5VSB - 70 - k Ω FAULT Output Impedance FAULT = high - 100 - Ω FAULT Under-Voltage Reporting Delay -10- µs TEMPERATURE MONITOR Fault-Level Threshold Note 3 125 - - oC Shutdown-Level Threshold Note 3 - 150 - oC NOTES: 2. Guaranteed by Correlation. 3. Guaranteed by Design. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS HIP6501A |
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