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HIP6303 Datasheet(PDF) 12 Page - Intersil Corporation

Part No. HIP6303
Description  Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

HIP6303 Datasheet(HTML) 12 Page - Intersil Corporation

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12
Droop, Selection of RIN
The average of the currents detected through the RISEN
resistors is also steered to the FB pin. There is no DC return
path connected to the FB pin except for RIN, so the average
current creates a voltage drop across RIN. This drop
increases the apparent VCORE voltage with increasing load
current, causing the system to decrease VCORE to maintain
balance at the FB pin. This is the desired “droop” voltage
used to maintain VCORE within limits under transient
conditions.
With a high dv/dt load transient, typical of high performance
microprocessors, the largest deviations in output voltage
occur at the leading and trailing edges of the load transient.
In order to fully utilize the output-voltage tolerance range, the
output voltage is positioned in the upper half of the range
when the output is unloaded and in the lower half of the
range when the controller is under full load. This droop
compensation allows larger transient voltage deviations and
thus reduces the size and cost of the output filter
components.
RIN should be selected to give the desired “droop” voltage at
the normal full load current 50
µA applied through the RISEN
resistor (or at a different full load current if adjusted as under
“Over-Current, Selecting RISEN” above).
RIN = Vdroop / 50µA
For a Vdroop of 80mV, RIN = 1.6kΩ
A resistor from the feedback pin to ground raises the output
voltage above VID when the output is unloaded. The offset
resistor, (Ros), is selected based on RIN and the amount of
desired no-load offset, (VOS).
Ros = RIN x VID / VOS
Current Balancing
The detected currents are also used to balance the channel
currents.
Each channel’s current is compared to the average of all
channel currents, and the difference is used to create an
offset in that channel’s PWM comparator. The offset is in a
direction to reduce the imbalance.
The balancing circuit can not make up for a difference in
rDS(ON) between synchronous rectifiers. If a FET has a
higher rDS(ON), the current through that channel will be
reduced.
Figures 8 and 9 show the inductor current of a two channel
system without and with current balancing.
Inductor Current
The inductor current in each channel of a multi-phase Buck
converter has two components. There is a current equal to
the load current divided by the number of channels (ILT / n),
and a sawtooth current, (iPK-PK) resulting from switching.
The sawtooth component is dependent on the size of the
inductors, the switching frequency of each channel, and the
values of the input and output voltage. Ignoring secondary
effects, such as series resistance, the peak to peak value of
the sawtooth current can be described by:
iPK-PK = (VIN x VCORE - VCORE
2) / (L x F
SW x VIN)
Where: VCORE = DC value of the output or VID voltage
VIN = DC value of the input or supply voltage
L = value of the inductor
FSW = switching frequency
Example: For VCORE = 1.6V,
VIN = 12V,
L = 1.3
µH,
FSW = 250kHz,
Then iPK-PK = 4.3A
0
5
10
15
20
25
FIGURE 8. TWO CHANNEL MULTIPHASE SYSTEM WITH
CURRENT BALANCING DISABLED
0
5
10
15
20
25
FIGURE 9. TWO CHANNEL MULTIPHASE SYSTEM WITH
CURRENT BALANCING ENABLED
HIP6303


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