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Layout Considerations

FIGURE 6. TYPICAL SCHEMATIC

CAP

OUT

GND

EN

SNS

PGND

P5V

0.1

µ

100

µ

10V

3x

1

µ

16V

+

RTN

4

8

5

3

2

6

7

1

8200p

RTN

5x

100

µ

10V

+

CERAMIC DECOUPLING

FOR HIGH di/dt LOAD

(MAY NOT BE REQUIRED)

BULK OUTPUT CAPACITANCE

OF DC-DC CONVERTER

OUTPUT OF DC-DC

(OUTPUT INDUCTOR)

FROM

µP CORE

HIP6201

U3

Example Layout

• HIP6200 located near bulk output capacitance (not shown is the microprocessor load itself - for best performance, the

HIP6200 and bulk output capacitance should be located close to the

µP)

TOP - SILK SCREEN

TOP - COMPONENT SIDE

SOLDER SIDE

INTERNAL ONE

NOTE: Internal layers are shown as negatives

(white is copper):

via connection to copper plane

no connection

GND

HIP6200, HIP6201