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HIP6200CB Datasheet(PDF) 9 Page - Intersil Corporation |
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HIP6200CB Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 9 page 2-449 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Layout Considerations FIGURE 6. TYPICAL SCHEMATIC CAP VCC PVCC OUT GND EN SNS PGND P5V C39 C38 0.1 µ C37 100 µ 10V C24-26 3x 1 µ 16V + RTN VOUT 4 8 5 3 2 6 7 1 8200p RTN C19-23 5x 100 µ 10V + CERAMIC DECOUPLING FOR HIGH di/dt LOAD (MAY NOT BE REQUIRED) BULK OUTPUT CAPACITANCE OF DC-DC CONVERTER OUTPUT OF DC-DC (OUTPUT INDUCTOR) FROM µP CORE HIP6201 U3 Example Layout • HIP6200 located near bulk output capacitance (not shown is the microprocessor load itself - for best performance, the HIP6200 and bulk output capacitance should be located close to the µP) •C37 (+5V bulk cap) located near the HIP6200 • Solid ground and VOUT planes with numerous via interconnects TOP - SILK SCREEN TOP - COMPONENT SIDE SOLDER SIDE INTERNAL ONE NOTE: Internal layers are shown as negatives (white is copper): via connection to copper plane no connection GND HIP6200, HIP6201 |
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Similar Description - HIP6200CB |
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