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HIP6020A Datasheet(PDF) 8 Page - Intersil Corporation |
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HIP6020A Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 16 page 4-8 The remaining outputs are also programmed to follow the SS pin voltage. The PGOOD signal toggles ‘high’ when all output voltage levels have exceeded their under-voltage levels. See the Soft-Start Interval section under Applications Guidelines for a procedure to determine the soft-start interval. Fault Protection All four outputs are monitored and protected against extreme overload. A sustained overload on any output or an over- voltage on VOUT1 output (VSEN1) disables all outputs and drives the FAULT/RT pin to VCC. Figure 7 shows a simplified schematic of the fault logic. An over-voltage detected on VSEN1 immediately sets the fault latch. A sequence of three over-current fault signals also sets the fault latch. The over-current latch is set dependent upon the states of the over-current (OC1 and OC2), linear under-voltage (LUV) and the soft-start signals. A window comparator monitors the SS pin and indicates when CSS is fully charged to 4.5V (UP signal). An under-voltage on either linear output (sensed at FB3 and FB4) is ignored until after the soft-start interval (T4 in Figure 6). This allows VOUT3 and VOUT4 to increase without fault at start-up. Cycling the bias input voltage (+12VIN on the VCC pin off then on) resets the counter and the fault latch. Over-Voltage Protection During operation, a short across the synchronous PWM upper MOSFET (Q1) causes VOUT1 to increase. When the output exceeds the over-voltage threshold of 115% of DACOUT, the over-voltage comparator trips to set the fault latch and turns the lower MOSFET (Q2) on. This blows the input fuse and reduces VOUT1. The fault latch raises the FAULT/RT pin to VCC. A separate over-voltage circuit provides protection during the initial application of power. For voltages on the VCC pin below the power-on reset (and above ~4V), the output level is monitored for voltages above 1.3V. Should VSEN1 exceed this level, the lower MOSFET, Q2 is driven on. Over-Current Protection All outputs are protected against excessive over-currents. Both PWM controllers use the upper MOSFET’s on- resistance, rDS(ON) to monitor the current for protection against shorted outputs. Both linear regulators monitor their respective VSEN pins for under-voltage to protect against excessive currents. Figure 8 illustrates the over-current protection with an overload on OUT2. The overload is applied at T0 and the current increases through the inductor (LOUT2). At time T1, the OVER-CURRENT2 comparator trips when the voltage across Q3 (iD • rDS(ON)) exceeds the level programmed by ROCSET. This inhibits all outputs, discharges the soft-start capacitor (CSS) with a 28µA current sink, and increments the counter. CSS recharges at T2 and initiates a soft-start cycle with the error amplifiers clamped by soft-start. With OUT2 still overloaded, the inductor current increases to trip the over- current comparator. Again, this inhibits all outputs, but the soft-start voltage continues increasing to 4.5V before discharging. The counter increments to 2. The soft-start cycle repeats at T3 and trips the over-current comparator. The SS pin voltage increases to 4.5V at T4 and the counter increments to 3. This sets the fault latch to disable the converter. The fault is reported on the FAULT/RT pin. The PWM1 controller operates in the same way as PWM2 to over-current faults. Additionally, the two linear controllers monitor the FB pins for an under-voltage. Should excessive currents cause FB3 or FB4 to fall below the linear under- voltage threshold, the LUV signal sets the over-current latch, providing CSS is fully charged. Blanking the LUV signal during the CSS charge interval allows the linear outputs to build above the under-voltage threshold during normal operation. Cycling the bias input power off then on resets the counter and the fault latch. FAULT LATCH S R Q POR COUNTER OC1 OV OC2 LUV + - + - 0.15V 4V SS VCC FAULT R FIGURE 4. FAULT LOGIC - SIMPLIFIED SCHEMATIC UP OVER- CURRENT LATCH INHIBIT S R Q FIGURE 5. OVER-CURRENT OPERATION 0A 0V 2V 4V TIME T1 T2 T3 T0 T4 0V 10V OVERLOAD APPLIED FAULT REPORTED COUNT = 1 COUNT = 2 COUNT = 3 HIP6020A |
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