7

Figure 5 shows the critical power components of the converter.

To minimize the voltage overshoot the interconnecting wires

indicated by heavy lines should be part of ground or power

plane in a printed circuit board. The components shown in

Figure 5 should be located as close together as possible.

numerous physical capacitors. Locate the HIP6004D within 3

MOSFETs’ gate and source connections from the HIP6004D

must be sized to handle up to 1A peak current.

Figure 6 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

close to the SS pin because the internal current source is

only 10

to the BOOT and PHASE pins.

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

the oscillator (OSC) triangular wave to provide a pulse-

the PHASE node.

The modulator transfer function is the small-signal transfer

peak-to-peak oscillator voltage

Modulator Break Frequency Equations

The compensation network consists of the error amplifier

a closed loop transfer function with the highest 0dB crossing

180 degrees

. The equations below relate the compensation

locating the poles and zeros of the compensation network:

6. Check Gain against Error Amplifier’s Open-Loop Gain.

7. Estimate Phase Margin - Repeat if Necessary.

PGND

LGATE

UGATE

PHASE

RETURN

HIP6004D

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

+12V

HIP6004D

SS

GND

VCC

BOOT

PHASE

FIGURE 7. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

REFERENCE

ESR

ERROR

AMP

PWM

DRIVER

(PARASITIC)

+

-

DACOUT

COMP

FB

HIP6004D

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

+

-

+

-

OSC

F

LC

1

2

π xL

O

xC

O

-------------------------------------------

=

F

ESR

1

2

π xESR xC

O

--------------------------------------------

=

HIP6004D