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HIP4081 Datasheet(PDF) 5 Page - Intersil Corporation

Part No. HIP4081
Description  80V/2.5A Peak, High Frequency Full Bridge FET Driver
Download  18 Pages
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HIP4081 Datasheet(HTML) 5 Page - Intersil Corporation

 
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5
Peak Pullup Current
IO+VOUT = 0V
1.7
2.6
3.8
1.4
4.1
A
Peak Pulldown Current
IO-VOUT = 12V
1.7
2.4
3.3
1.3
3.6
A
Electrical Specifications
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K
and TA = 25
oC, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TJ = 25
oC
TJS = -40
oC
TO 125oC
UNITS
MIN
TYP MAX
MIN
MAX
Switching Specifications
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K,
CL = 1000pF
PARAMETER
SYMBOL
TEST CONDITIONS
TJ = +25
oC
TJS = 40
oC
TO 125oC
UNITS
MIN
TYP
MAX
MIN
MAX
Lower Turn-off Propagation Delay
(ALI-ALO, BLI-BLO)
TLPHL
-
30
60
-
80
ns
Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)
THPHL
-
35
70
-
90
ns
Lower Turn-on Propagation Delay
(ALI-ALO, BLI-BLO)
TLPLH
-
45
70
-
90
ns
Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)
THPLH
-
60
90
-
110
ns
Rise Time
TR
-
10
25
-
35
ns
Fall Time
TF
-
10
25
-
35
ns
Turn-on Input Pulse Width
TPWIN-ON
50
-
-
50
-
ns
Turn-off Input Pulse Width
TPWIN-OFF
40
-
-
40
-
ns
Disable Turn-off Propagation Delay
(DIS - Lower Outputs)
TDISLOW
-
45
75
-
95
ns
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
TDISHIGH
-
55
85
-
105
ns
Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)
TDLPLH
-
35
70
-
90
ns
Refresh Pulse Width (ALO and BLO)
TREF-PW
160
260
380
140
420
ns
Disable to Upper Enable (DIS - AHO and BHO)
THEN
-
335
500
-
550
ns
TRUTH TABLE
INPUT
OUTPUT
ALI, BLI
AHI, BHI
DIS
ALO, BLO
AHO, BHO
XX
1
0
0
1X0
1
0
010
0
1
000
0
0
NOTE: X signifies that input can be either a “1” or “0”.
HIP4081


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