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HIP4080 Datasheet(PDF) 13 Page - Intersil Corporation

Part No. HIP4080
Description  80V/2.5A Peak, High Frequency Full Bridge FET Driver
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

HIP4080 Datasheet(HTML) 13 Page - Intersil Corporation

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13
HIP4080 Power-up Application Information
The HIP4080 H-Bridge Driver IC requires external circuitry
to assure reliable start-up conditions of the upper drivers. If
not addressed in the application, the H-Bridge power MOS-
FETs may be exposed to shoot-through current, possibly
leading to MOSFET failure. Following the instructions below
will result in reliable start-up.
The HIP4080 does not have an input protocol like the
HIP4081 that keeps both lower power MOSFETs off other
than through the DIS pin. IN+ and IN- are inputs to a com-
parator that control the bridge in such a way that only one of
the lower power devices is on at a time, assuming DIS is low.
However, keeping both lower MOSFETs off can be accom-
plished by controlling the lower turn-on delay pin, LDEL,
while the chip is enabled, as shown in Figure 32. Pulling
LDEL to VDD will indefinitely delay the lower turn-on delays
through the input comparator and will keep the lower MOS-
FETs off. With the lower MOSFETs off and the chip enabled,
i.e. DIS = low, IN+ or IN- can be switched through a full
cycle, properly setting the upper driver outputs. Once this is
accomplished, LDEL is released to its normal operating
point. It is critical that IN+/IN- switch a full cycle while LDEL
is held high, to avoid shoot-through. This start-up procedure
can be initiated by the supply voltage and/or the chip enable
command by the circuit in Figure 32.
11
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20
19
10
9
8
7
6
5
4
3
2
1 BHB
HEN
DIS
VSS
OUT
IN+
HDEL
IN-
LDEL
AHB
BHO
BLO
BLS
VDD
BHS
VCC
ALS
ALO
AHS
AHO
100K
RDEL
RDEL
VDD
0.1
µF
2N3906
VDD
ENABLE
VDD
56K
8.2V
56K
100K
FIGURE 32.
VDD
DIS
LDEL
=10ms
t1
t2
8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE)
12V, FINAL VALUE
5.1V
NOTES:
2. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If
the ENABLE pin is low after the under-voltage circuit is satisfied, the ENABLE pin will initiate the 10ms time delay during which the IN+
and IN- pins must cycle at least once.
3. Another product, HIP4080A, incorporates undervoltage circuitry which eliminates the need for the above power up circuitry.
FIGURE 33. TIMING DIAGRAM FOR FIGURE 32
HIP4080


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