ADF7025

Data Sheet

Rev. B | Page 36 of 44

REGISTER 8—POWER-DOWN TEST REGISTER

PD1

PD2

PD3

PD4

PD5

DB8

DB7

DB6

DB5

DB4

DB3

DB2

C2(0)

C1(0)

CONTROL

BITS

DB1

DB0

C3(0)

C4(1)

LOG AMP/

RSSI

PD7

DB15

DB14

DB13

DB12

DB11

LR1

PD6

DB10

DB9

LR2

SW1

PD7

0

1

PA (Rx MODE)

PA OFF

PA ON

SW1

0

1

Tx/Rx SWITCH

DEFAULT (ON)

OFF

PD6

0

1

DEMOD ENABLE

DEMOD OFF

DEMOD ON

PD5

0

1

ADC ENABLE

ADC OFF

ADC ON

LR2

X

X

LR1

0

1

RSSI MODE

RSSI OFF

RSSI ON

PD4

0

1

FILTER ENABLE

FILTER OFF

FILTER ON

PD3

0

1

LNA/MIXER ENABLE

LNA/MIXER OFF

LNA/MIXER ON

PLE1

(FROM REG 0)

0

0

0

0

1

PD2

0

0

1

1

X

LOOP

CONDITION

VCO/PLL OFF

PLL ON

VCO ON

PLL/VCO ON

PLL/VCO ON

PD1

0

1

0

1

X

Figure 47. Register 8—Power-Down Test Register

Register 8—Power-Down Test Register Comments

• For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition.

• It is not necessary to write to this register under normal operating conditions.