ADF7021_15 datasheet(47/62 Pages) AD

Part #	ADF7021

Description	High Performance Narrow-Band Transceiver IC

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Data Sheet

ADF7021

Rev. C | Page 47 of 62

REGISTER 0—N REGISTER

Figure 62. Register 0—N Register Map

The RF output frequency is calculated by the following:

For the direct output



















15

2

_

N

Fractional

N

Integer

PFD

RF

OUT

For the RF_DIVIDE_BY_2 (DB18) selected



















15

2

_

5

.

0

N

Fractional

N

Integer

PFD

RF

OUT

In UART/SPI mode, the TxRxCLK pin is used to input the Tx

data. The Rx Data is available on the TxRxDATA pin.

In the MUXOUT map in Figure 62, the

FILTER_CAL_COMPLETE indicates when a coarse or coarse

plus fine IF filter calibration has finished. The

DIGITAL_LOCK_DETECT indicates when the PLL has locked.

The RSSI_READY indicates that the RSSI signal has settled and

an RSSI readback can be performed. Tx_Rx gives the status of

DB27 in this register, which can be used to control an external

Tx/Rx switch.

TR1

TRANSMIT/

RECEIVE

0

TRANSMIT

RECEIVE

1

M3

M2

M1

MUXOUT

0

REGULATOR_READY (DEFAULT)

FILTER_CAL_COMPLETE

0

DIGITAL_LOCK_DETECT

0

RSSI_READY

1

Tx_Rx

1

LOGIC_ZERO

1

TRISTATE

1

0

1

0

1

0

1

0

1

0

1

0

1

LOGIC_ONE

U1

UART MODE

0DISABLED

1

ENABLED

N8

N7

N6

N5

N4

N3

N2

N1

N COUNTER

DIVIDE RATIO

023

024

.

1253

1254

1

0

.

1

0

.

1

.

0

1

.

1

0

1

.

1

0

1

.

1

0

1

0

1255

15-BIT FRACTIONAL_N

8-BIT INTEGER_N

MUXOUT

ADDRESS

BITS

FRACTIONAL

DIVIDE RATIO

0

1

2

.

32764

32765

32766

32767

M15

0

.

1

M14

0

.

1

M13

0

.

1

...

M3

0

.

1

M2

0

1

.

0

1

M1

0

1

0

.

0

1

0

1

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