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ADF4002 Datasheet(PDF) 8 Page - Analog Devices |
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ADF4002 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 20 page  ADF4002 Data Sheet Rev. C | Page 8 of 20 THEORY OF OPERATION REFERENCE INPUT SECTION The reference input stage is shown in Figure 10. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. 100kΩ NC REFIN NC NO SW1 SW2 BUFFER SW3 TO R COUNTER POWER-DOWN CONTROL Figure 10. Reference Input Stage RF INPUT STAGE The RF input stage is shown in Figure 11. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the N counter. 500Ω 1.6V 500Ω AGND BIAS GENERATOR RFINA RFINB AVDD Figure 11. RF Input Stage N COUNTER The N CMOS counter allows a wide ranging division ratio in the PLL feedback counter. Division ratios from 1 to 8191 are allowed. N and R Relationship The N counter makes it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is R f N f REFIN VCO × = where: fVCO is the output frequency of external voltage controlled oscillator (VCO). N is the preset divide ratio of binary 13-bit counter (1 to 8191). fREFIN is the external reference frequency oscillator. TO PFD FROM RF INPUT STAGE FROM N COUNTER LATCH 13-BIT N COUNTER Figure 12. N Counter R COUNTER The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 13 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function, and minimizes phase noise and reference spurs. Two bits in the reference counter latch (ABP2 and ABP1) control the width of the pulse. See Figure 16 for details. The smallest antibacklash pulse width is not recommended. HI HI D1 D2 Q1 Q2 CLR1 CLR2 CP U1 U2 UP DOWN ABP2 ABP1 CPGND U3 R DIVIDER PROGRAMMABLE DELAY N DIVIDER VP CHARGE PUMP Figure 13. PFD Simplified Schematic and Timing (In Lock) |
Similar Part No. - ADF4002_15 |
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Similar Description - ADF4002_15 |
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