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HI2325 Datasheet(PDF) 3 Page - Intersil Corporation

Part No. HI2325
Description  3.3V Dual 8-Bit, 40MSPS A/D Converter with Internal Reference and Digital Clamp
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HI2325 Datasheet(HTML) 3 Page - Intersil Corporation

   
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3
Pin Descriptions
PIN NO.
SYMBOL
I/O
EQUIVALENT CIRCUIT
DESCRIPTION
46, 47, 48, 1- 5
A0 - A7
O
Digital Output. A0(LSB) - A7(MSB)
8 - 15
B0 - B7
O
Digital Output. B0(LSB) - B7(MSB)
6, 7
DVDD
Digital power supply.
16
DVSS
Digital ground.
17
2S/B
I
Pull-down resistors are
incorporated.
Selects output code.
H: 2’s Compliment Code L: Binary Code
18, 19, 20
REF0 ~ 2
I
Pull-down resistors are
incorporated.
Determines the clamp circuit reference data. See the table “Digital
Clamp Reference Level”.
21
TEST
I
Pull-down resistors are
incorporated.
Normally open.
22, 25
DVSS
Digital ground.
22, 25, 36
AVSS
Analog ground.
23
38
BRBS
ARBS
Shorting these pins to AVSS generates voltage of about 0.5V at the
BRB and ARB pins.
24
37
BRB
ARB
Reference voltage (bottom).
29
32
BRT
ART
Reference voltage (top).
30
31
BRTS
ARTS
Shorting these pins to AVDD generates voltage of about 2.5V at the
BRT and ART pins.
26
35
BIO
AIO
O
Analog output. The digital clamp circuit comprises a D/A converter
whose outputs are available on these pins.
27
34
BIN
AIN
I
Analog input.
28, 33, 39
AVDD
Analog power supply.
40
STB
I
Pull-down resistors are
incorporated.
Stand-by input.
H: Stand-by mode L: Operation mode.
41
SEL
I
Pull-down resistors are
incorporated.
Controls the CLP signal polarity.
H: CLP is High active L: CLP is Low active.
42
CLE
I
Pull-down resistors are
incorporated.
Clamp enable input.
H: Enable L: Disable.
43
CLP
I
Pull-down resistors are
incorporated.
Clamp pulse input. The polarity can be set to either High or Low by
setting SEL.
44
CLK
I
Pull-down resistors are
incorporated.
Clock input.
HI2325


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