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AD73360L Datasheet(PDF) 3 Page - Analog Devices

Part No. AD73360L
Description  Six-Input Channel Analog Front End
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD73360L Datasheet(HTML) 3 Page - Analog Devices

 
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REV. 0
–3–
AD73360L
AD73360LA
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC OUTPUT
VOH, Output High Voltage
VDD – 0.4
VDD
V
|IOUT|
≤ 100 µA
VOL, Output Low Voltage
0
0.4
V
|IOUT|
≤ 100 µA
Three-State Leakage Current
–10
+10
µA
POWER SUPPLIES
AVDD1, AVDD2
2.7
3.6
V
DVDD
2.7
3.6
V
IDD
8
See Table I
NOTES
1Operating temperature range is as follows: –40
°C to +85°C. Therefore, T
MIN = –40
°C and T
MAX = +85
°C.
2Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).
3At input to sigma-delta modulator of ADC.
4Guaranteed by design.
5Overall group delay will be affected by the sample rate and the external digital filtering.
6The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4
× 1011)/DMCLK.
7Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
8Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground.
Specifications subject to change without notice.
Table I. Current Summary (AVDD = DVDD = 3.3 V)
Total
Current
MCLK
Conditions
(Max)
SE
ON
Comments
ADCs Only On
25
1
Yes
REFOUT Disabled
REFCAP Only On
1.0
0
No
REFOUT Disabled
REFCAP and REFOUT Only On
3.5
0
No
All Sections On
26.5
1
Yes
REFOUT Enabled
All Sections Off
1.0
0
Yes
MCLK Active Levels Equal to 0 V and DVDD
All Sections Off
0.05
0
No
Digital Inputs Static and Equal to 0 V or DVDD
The above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz.
TIMING CHARACTERISTICS
Limit at
Parameter
TA = –40 C to +85 C
Unit
Description
Clock Signals
See Figure 1.
t1
61
ns min
MCLK Period
t2
24.4
ns min
MCLK Width High
t3
24.4
ns min
MCLK Width Low
Serial Port
See Figures 3 and 4.
t4
t1
ns min
SCLK Period
t5
0.4
× t1
ns min
SCLK Width High
t6
0.4
× t1
ns min
SCLK Width Low
t7
20
ns min
SDI/SDIFS Setup before SCLK Low
t8
0
ns min
SDI/SDIFS Hold after SCLK Low
t9
10
ns max
SDOFS Delay from SCLK High
t10
10
ns max
SDOFS Hold after SCLK High
t11
10
ns max
SDO Hold after SCLK High
t12
10
ns max
SDO Delay from SCLK High
t13
30
ns max
SCLK Delay from MCLK
(AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; TA = TMlN to TMAX, unless other-
wise noted.)


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