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AD73360L Datasheet(PDF) 12 Page - Analog Devices

Part No. AD73360L
Description  Six-Input Channel Analog Front End
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD73360L Datasheet(HTML) 12 Page - Analog Devices

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AD73360L
–12–
Table VI. Control Register B Description
76543210
C E E
MCD2
MCD1
MCD0
SCD1
SCD0
DR1
DR0
Bit Name
Description
0
DR0
Decimation Rate (Bit 0)
1
DR1
Decimation Rate (Bit 1)
2
SCD0
Serial Clock Divider (Bit 0)
3
SCD1
Serial Clock Divider (Bit 1)
4
MCD0
Master Clock Divider (Bit 0)
5
MCD1
Master Clock Divider (Bit 1)
6
MCD2
Master Clock Divider (Bit 2)
7
CEE
Control Echo Enable (0 = OFF; 1 = Enabled)
Table VII. Control Register C Description
76543210
RES
RU
PUREF
RES
RES
RES
RES
GPU
Bit Name
Description
0
GPU
Global Power-Up Device (0 = Power Down; 1 = Power Up)
1
Reserved
Must Be Programmed to Zero (0)
2
Reserved
Must Be Programmed to Zero (0)
3
Reserved
Must Be Programmed to Zero (0)
4
Reserved
Must Be Programmed to Zero (0)
5
PUREF
REF Power (0 = Power Down; 1 = Power Up)
6
RU
REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)
7
Reserved
Must Be Programmed to Zero (0)
Table VIII. Control Register D Description
76543210
PUI2
I2GS2
I2GS1
I2GS0
PUI1
I1GS2
I1GS1
I1GS0
Bit Name
Description
0
I1GS0
ADC1:Input Gain Select (Bit 0)
1
I1GS1
ADC1:Input Gain Select (Bit 1)
2
I1GS2
ADC1:Input Gain Select (Bit 2)
3
PUI1
Power Control (ADC1); 1 = ON, 0 = OFF
4
I2GS0
ADC2:Input Gain Select (Bit 0)
5
I2GS1
ADC2:Input Gain Select (Bit 1)
6
I2GS2
ADC2:Input Gain Select (Bit 2)
7
PUI2
Power Control (ADC2); 1 = ON, 0 = OFF
CONTROL REGISTER B
CONTROL REGISTER D
CONTROL REGISTER C


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