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AD73360L Datasheet(PDF) 6 Page - Analog Devices

Part No. AD73360L
Description  Six-Input Channel Analog Front End
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD73360L Datasheet(HTML) 6 Page - Analog Devices

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REV. 0
AD73360L
–6–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
VINP2
Analog Input to the Positive Terminal of Input Channel 2.
2
VINN2
Analog Input to the Negative Terminal of Input Channel 2.
3
VINP1
Analog Input to the Positive Terminal of Input Channel 1.
4
VINN1
Analog Input to the Negative Terminal of Input Channel 1.
5
REFOUT
Buffered Output of the Internal Reference, which has a nominal value of 1.2 V.
6
REFCAP
Reference Voltage for ADCs. A Bypass Capacitor to AGND2 of 0.1
µF is required for the on-chip
reference. The capacitor should be fixed to this pin. The internal reference can be overdriven by an
external reference connected to this pin if required.
7
AVDD2
Analog Power Supply Connection.
8
AGND2
Analog Ground/Substrate Connection.
9
DGND
Digital Ground/Substrate Connection.
10
DVDD
Digital Power Supply Connection.
11
RESET
Active Low-Reset Signal. This input resets the entire chip, resetting the control registers and clearing
the digital circuitry.
12
SCLK
Output Serial Clock, whose rate determines the serial transfer rate to/from the AD73360L. It is used
to clock data or control information to and from the serial port (SPORT). The frequency of SCLK is
equal to the frequency of the master clock (MCLK) divided by an integer number—this integer num-
ber being the product of the external master clock rate divider and the serial clock rate divider.
13
MCLK
Master Clock Input. MCLK is driven from an external clock signal.
14
SDO
Serial Data Output of the AD73360L. Both data and control information may be output on this
pin and are clocked on the positive edge of SCLK. SDO is in three-state when no information is being
transmitted and when SE is low.
15
SDOFS
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one
SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive
edge of SCLK. SDOFS is in three-state when SE is low.
16
SDIFS
Framing Signal Input for SDI Serial Transfers. The frame sync is one-bit wide and it is valid one
SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of
SCLK and is ignored when SE is low.
17
SDI
Serial Data Input of the AD73360L. Both data and control information may be input on this pin and
are clocked on the negative edge of SCLK. SDI is ignored when SE is low.
18
SE
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the
output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled inter-
nally in order to decrease power dissipation. When SE is brought high, the control and data registers of
the SPORT are at their original values (before SE was brought low); however, the timing counters and
other internal registers are at their reset values.
19
AGND1
Analog Ground Connection.
20
AVDD1
Analog Power Supply Connection.
21
VINP6
Analog Input to the Positive Terminal of Input Channel 6.
22
VINN6
Analog Input to the Negative Terminal of Input Channel 6.
23
VINP5
Analog Input to the Positive Terminal of Input Channel 5.
24
VINN5
Analog Input to the Negative Terminal of Input Channel 5.
25
VINP4
Analog Input to the Positive Terminal of Input Channel 4.
26
VINN4
Analog Input to the Negative Terminal of Input Channel 4.
27
VINP3
Analog Input to the Positive Terminal of Input Channel 3.
28
VINN3
Analog Input to the Negative Terminal of Input Channel 3.


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