AD71028

Rev. 0 | Page 14 of 20

Table 13. SPI Control Register 1 Write format

Byte 0

Byte 1

Byte 2

Byte 3

00000, Wb/R, Adr [9:8]

Adr [7:0]

00000, Bit [10:8]

Bit [7:0]

Table 14. SPI Write Format for Parameter RAM, Output Level, Stereo Spreading and Dialog Enhancement Registers

Byte 0

Byte1

Byte 2

Byte 3

Byte 4

000000, Adr [9:8]

Adr [7:0]

00, Level [21:16]

Level [15:8]

Level [7:0]

SPI READ/WRITE DATA FORMATS

The read/write formats of the SPI port are designed to be byte-

oriented. This allows for easy programming of common micro-

controller chips. In order to fit into a byte-oriented format, 0s

are appended to the data fields in order to extend the data-word

to the next multiple of 8 bits. For example, 22-bit words written

to the SPI parameter RAM are appended with two leading zeros

in order to reach 24 bits (3 bytes). These zero-extended data

fields are appended to a 2-byte field consisting of a read/write

bit and a 10-bit address. The SPI port knows how many data

bytes to expect based on the address that is received in the first

2 bytes.

INITIALIZATION

Power-Up Sequence

The AD71028 has a built-in power-up sequence that initializes

the contents of all internal RAM. During this time, the SPI

parameter RAM is filled with values from its associated boot

ROM. The data memories are also cleared during this time.

The boot sequence lasts for 1024 MCLK cycles and starts on the

rising edge of the RESETB pin. The user should avoid writing to

or reading from the SPI registers during this period of time.

SERIAL DATA INPUT PORT

The AD71028’s flexible serial data input port accepts data in

twos complement, MSB-first format. The left channel data field

always precedes the right channel data field. The serial mode is

set by using mode select bits in the SPI control register. In all

modes except the right-justified mode, the serial port will

accept an arbitrary number of bits up to a limit of 24 (extra bits

will not cause an error, but they will be truncated internally). In

right-justified mode, SPI control register bits are used to set the

word length to 16, 20, or 24 bits. The default on power-up is

24-bit mode. Proper operation of the right-justified mode

requires that there be exactly 64 BCLKs per audio frame.

Serial Data Input Modes

Figure 7 shows the left-justified mode. LRCLK is high for the

left channel and low for the right channel. Data is sampled on

the rising edge of BCLK. The MSB is left-justified to a LRCLK

transition with no MSB delay. The left-justified mode can accept

any word length up to 24 bits.

LRCLK is low for the left channel, and the MSB is delayed from

can be used to accept any number of bits up to 24.

Figure 9 shows the AD71028’s right-justified mode. LRCLK is

high for the left channel and low for the right channel. Data is

sampled on the rising edge of BCLK. The start of data is delayed

from the LRCLK edge by 16, 12, or 8 BCLK intervals, depending

on the selected word length. The default word length is 24 bits;

other word lengths are set by writing to Bits <1:0> of the control

register. In right-justified mode, it is assumed that there are 64

BCLKs per frame.

Figure 10 shows the DSP serial port mode. LRCLK must pulse

high for at least one bit clock period before the MSB of the left

channel is valid, and LRCLK must pulse high again for at least

one bit clock period before the MSB of the right channel is

valid. Data is sampled on the falling edge of BCLK. The DSP

serial port mode can be used with any word length up to 24 bits.

In this mode, it is the responsibility of the DSP to ensure that

the left data is transmitted with the first LRCLK pulse, and that

synchronism is maintained from that point forward.