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AD10678 Datasheet(PDF) 14 Page - Analog Devices

Part No. AD10678
Description  16-Bit, 80 MSPS A/D Converter
Download  20 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD10678 Datasheet(HTML) 14 Page - Analog Devices

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AD10678
Rev. C | Page 14 of 20
The +3.3 VE supply provides power to the clock distribution
circuit. The +3.3 VD supply provides power to the digital
output section of the ADCs, the PECL-to-TTL translator, and
the CPLD. Separate +3.3 VE and +3.3 VD supplies are used to
prevent modulation of the clock signal with digital noise.
The +5.0 VA supply provides power to the analog sections
of the ADCs. Decoupling capacitors are strategically placed
throughout the circuit to provide low impedance noise shunts
to ground. The +5.0 VA supply (analog power) should be
decoupled to analog ground (AGND), and +3.3 VD (digital
power) should be decoupled to digital ground (DGND). The
+3.3 VE supply (analog power) should be decoupled to AGND.
The evaluation board schematic and layout data provide a
typical PCB implementation of the AD10678. Table 8 shows the
PCB bill of materials.
ANALOG AND DIGITAL GROUNDING
Although the AD10678 provides separate analog and digital
ground pins, the device should be treated as an analog
component. Proper grounding is essential in high speed, high
resolution systems. Multilayer printed circuit boards are
recommended to provide optimal grounding and power
distribution. The use of power and ground planes provides
distinct advantages. Power and ground planes minimize the
loop area encompassed by a signal and its return path,
minimize the impedance associated with power and ground
paths, and provide a distributed capacitor formed by the power
plane, printed circuit board material, and ground plane. The
AD10678 unit has four metal standoffs (see Figure 10). MH2 is
located in the center of the unit and MH1 is located directly
below analog header P3. Both of these standoffs are tied to
analog ground and should be connected accordingly on the
next level assembly for optimum performance. The two
standoffs located near P1 and P2 (MH3 and MH4) are tied to
digital ground and should be connected accordingly on the
next-level assembly.
OTHER NOTES
The circuit is configured on a 2.2 inch × 2.8 inch laminate
board with three sets of connector interface pads. The pads
are configured to provide easy keying for the user. The pads
are made for low profile applications and have a total height of
0.12 inches after mating. The part numbers for the header mates
are provided in Figure 10. All pins of the analog and digital
sections are described in the Pin Configurations and Function
Descriptions section.
EVALUATION BOARD
The AD10678 evaluation board provides an easy way to test
the 16-bit, 80 MSPS ADC. The board requires a clock source,
an analog input signal, two 3.3 V power supplies, and a 5 V
power supply. The clock source is buffered on the board to
provide a latch, a data ready signal, and the clock for the
AD10678. To use the AD10678 data ready output to clock
the buffer memory, remove R24 (0.0 Ω) and install a 0.0 Ω
resistor at R31 (DNI). The ADC digital outputs are latched on
board by a 74LCX16374. The digital outputs and output clock
are available on a 40-pin connector, J1. Power is supplied to the
board via uninsulated metal banana jacks.
The analog input is connected via an SMA connector, AIN. The
analog input section provides a single-ended input option or a
differential input option. The board is shipped in a single-ended
analog input option. Removing a ground tie at E17 converts the
circuit to a differential analog input configuration.
Table 8. PCB Bill of Materials
Item
Quantity
Reference Designator
Description
1
1
J1
Connector, 40-position header, male straight
2
1
U1
IC, LV 16-bit, D-type flip-flop with 5 V tolerant I/O
3
3
L1 to L3
Common-mode surface-mount ferrite bead 20 Ω
4
3
J11 to J13
Connector, 1 mm single-element interface
5
6
P1, P2, P8 to P10, P12
Uninsulated banana jack, all metal
6
2
U5, U6
IC, 3.3 V/5 V ECL differential receiver/driver
7
1
U7
IC, 3.3 V dual differential LVPECL to LVTTL translator
8
1
R24
RES 0.0 Ω 1/10 W 5% 0805 SMD
9
19
R0 to R16, R20, R23
RES 51.1 Ω 1/10 W 1% 0805 SMD
10
1
R17
RES 18.2 kΩ 1/10 W 1% 0805 SMD
11
4
R18, R19, R21, R22
RES 100 Ω 1/10 W 1% 0805 SMD
12
17
C1, C10 to C13, C16 to C18, C23 to C26, C28 to C32
CAP 0.1 μF 16 V ceramic X7R 0805
13
6
C8, C9, C4, C15, C27, C33
CAP 10 μF 10 V ceramic Y5V 1206
14
4
J2, J3, J5, J6
Connector, SMA jack 200 Mil STR gold
15
1
A1
Assembly, AD10678BWS
16
1
AD106xx Evaluation Board
GS04483 (PCB)


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