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AD10678 Datasheet(PDF) 13 Page - Analog Devices
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AD10678 Datasheet(HTML) 13 Page - Analog Devices
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Preliminary Technical Data
Rev. C | Page 13 of 20
THEORY OF OPERATION
The AD10678 uses four parallel, high speed ADCs in a
correlation technique to improve the dynamic range of the
ADCs. The technique consists of summing the parallel outputs
of the four converters to reduce the uncorrelated noise
introduced by the individual converters. Signals processed
through the high speed adder are correlated and summed
coherently. Noise is not correlated and sums on an rms basis.
The four high speed ADCs use a three-stage subrange architec-
ture. The AD10678 provides complementary analog input pins,
AIN and AIN. Each analog input is centered around 2.4 V and
should swing ±0.55 V around the reference. Because AIN and
AIN are 180 degrees out of phase, the differential analog input
signal is 2.15 V p-p.
The analog input is designed for a 50 Ω input impedance for
easy interface to commercially available cables, filters, drivers,
and so on.
The AD10678 encode inputs are ac-coupled to a PECL
differential receiver/driver. The output of the receiver/driver
provides a clock source for a 1:5 PECL clock driver and a PECL-
to-TTL translator. The 1:5 PECL clock driver provides the
differential encode signal for each of the four high speed ADCs.
The PECL-to-TTL translator provides a clock source for the
complex programmable logic device (CPLD).
The digital outputs from the four ADCs drive 120 Ω series
output terminators and are applied to the CPLD for post-
processing. The digital outputs are added together in the
complex programmable logic device through a ripple-carry
adder, which provides the 16-bit data output. The AD10678
provides valid data following 10 pipeline delays. The result
is a 16-bit parallel digital CMOS-compatible word coded as
Due to the high power nature of the part, it is critical that the
following thermal conditions be met for the part to perform to
data sheet specifications. This also ensures that the maximum
junction temperature (150°C) is not exceeded.
Operation temperature (T
) must be within 0°C to 70°C.
All mounting standoffs should be fastened to the interface
PCB assembly with 2-56 nuts. This ensures good thermal
paths as well as excellent ground points.
The unit rises to ~72°C (T
) on the heat sink in still air
(0 linear feet per minute (LFM)). The minimum
recommended air flow is 100 linear feet per minute (LFM)
in either direction across the heat sink (see Figure 21).
AIR FLOW (AMBIENT) (LFM)
Figure 21. Temperature (Case) vs. Air Flow (Ambient)
The user is provided with a single-to-differential transformer-
coupled input. The input impedance is 50 Ω and requires a
2.15 V p-p input level to achieve full scale.
ENCODING THE AD10678
The AD10678 encode signal must be a high quality, low phase
noise source to prevent performance degradation. The clock
input must be treated as an analog input signal because aperture
jitter can affect dynamic performance. For optimum perform-
ance, the AD10678 must be clocked differentially.
Take care when designing the data receivers for the AD10678.
The complex, programmable logic device, 16-bit outputs drive
120 Ω series resistors to limit the amount of current that can
flow into the output stage. To minimize capacitive loading,
there should be only one gate on each of the output pins. A
typical CMOS gate combined with the PCB trace has a load of
approximately 10 pF. Note that extra capacitive loading
increases output timing and invalidates timing specifications.
Digital output timing is guaranteed with a 10 pF load.
ANALOG AND DIGITAL POWER SUPPLIES
Care must be taken when selecting a power source. Linear
supplies are recommended. Switching supplies tend to have
radiated components that can be coupled into the ADCs. The
AD10678 features separate analog and digital supply and
ground currents, helping to minimize digital corruption of
sensitive analog signals.
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