HFA3861B datasheet(19/36 Pages) INTERSIL

Part #	HFA3861B

Description	Direct Sequence Spread Spectrum Baseband Processor

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Manufacturer	INTERSIL [Intersil Corporation]

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19

Clock Offset Tracking Performance

The PRISM baseband processor is designed to accept

data clock offsets of up to ±25ppm for each end of the link

(TX and RX). This effects both the acquisition and the

tracking performance of the demodulator. The budget for

clock offset error is 0.75dB at ±50ppm. No appreciable

degradation was seen for operation in AWGN at ±50ppm.

Carrier Offset Frequency Performance

The correlators used for acquisition for all modes and for

demodulation in the 1 and 2Mbps modes are time invariant

matched ﬁlter correlators otherwise known as parallel

correlators. They use two samples per chip and are tapped

at every other shift register stage. Their performance with

carrier frequency offsets is determined by the phase roll rate

due to the offset. For an offset of +50ppm (combined for both

TX and RX) will cause the carrier to phase roll 22.5 degrees

over the length of the correlator. This causes a loss of

0.22dB in correlation magnitude which translates directly to

Eb/N0 performance loss. In the PRISM chip design, the

carrier phase locked loop is inactive during acquisition.

During tracking, the carrier tracking loop corrects for offset,

so that no degradation is noted. In the presence of high

multipath and high SNR, however, some degradation is

expected.

FIGURE 14. BER vs Eb/N0 PERFORMANCE FOR PSK MODES

FIGURE 15. BER vs Eb/N0 PERFORMANCE FOR CCK MODES

789

10

11

12

Eb/N0

1.E+00

1.E-03

1.E-04

1.E-05

1.E-07

1.E-08

1.E-02

1.E-06

1.E-01

BER 1.0

BER 2.0

THY 1, 2

14

13

12

11

10

9

8

7

6

5

Eb/N0

1.E+00

1.E-03

1.E-04

1.E-05

1.E-07

1.E-08

1.E-02

1.E-06

1.E-01

1.E-09

BER 11

BER 5.5

THY 5.5

THY 11

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