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HFA3860 Datasheet(PDF) 21 Page - Intersil Corporation |
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HFA3860 Datasheet(HTML) 21 Page - Intersil Corporation |
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21 / 40 page  4- 21 The second form of correlator is the serial correlator bank used for detection of the MBOK modulation. There is a bank of eight 8 chip correlators for the I Channel and another 8 for the Q Channel. These correlators integrate over the symbol and are sampled at the symbol rate of 1.375 MSPS. Each bank of correlators is connected to a biggest picker that finds the correlator output with the largest magnitude output. This finding of 1 out of 8 process determines 3 signal bits per correlator bank. The sign of the correlator output determines 1 more bit per bank. Thus, each bank of correlators can determine 4 bits at 1.375 MSPS. This is a rate of 5.5 Mbps. Only the I correlator bank is used for BMBOK. When both correlator banks are used, this becomes twice that rate or 11 Mbps. Data Demodulation and Tracking Description (DBPSK and DQPSK Modes) The signal is demodulated from the correlation peaks tracked by the symbol timing loop (bit sync) as shown in Figure 15. The frequency and phase of the signal is corrected from the NCO that is driven by the phase locked loop. Demodulation of the DPSK data in the early stages of acquisition is done by delay and subtraction of the phase samples. Once phase locked loop tracking of the carrier is established, coherent demodulation is enabled for better performance. Averaging the phase errors over 16 symbols gives the necessary frequency information for proper NCO operation. The signal quality known as SQ2 is the variance in this estimate. Configuration Register 15 sets the search timer for the SFD. This register sets this time-out length in symbols for the receiver. If the time out is reached, and no SFD is found, the receiver resets to the acquisition mode. The suggested value is # preamble symbols + 16. If several transmit preamble lengths are used by various transmitters in a network, the longest value should be used for the receiver settings. Data Decoder and Descrambler Description The data decoder that implements the desired DQPSK coding/decoding as shown in Table 10. The data is formed into pairs of bits called dibits. The left bit of the pair is the first in time. This coding scheme results from differential coding of the dibits. Vector rotation is counterclockwise for a positive phase shift, but can be reversed with bit 5 or 6 of CR2. For DBPSK, the decoding is simple differential decoding. The data scrambler and de-scrambler are self synchronizing circuits. They consist of a 7-bit shift register with feedback of some of the taps of the register. The scrambler is designed to insure smearing of the discrete spectrum lines produced by the PN code. One thing to keep in mind is that both the differential decoding and the descrambling cause error extension. This causes the errors to occur in groups of 4 and 6. This is due to two properties of the processing. First, the differential decoding process causes errors to occur in pairs. When a symbol error is made, it is usually a single bit error even in QPSK mode. When a symbol is in error, the next symbol will also be decoded wrong since the data is encoded in the change from one symbol to the next. Thus, two errors are made on two successive symbols. In QPSK mode, these may be next to one another or separated by up to 2 bits. Secondly, when the bits are processed by the descrambler, these errors are further extended. The descrambler is a 7-bit shift register with one or more taps exclusive or’ed with the bit stream. If for example the scrambler polynomial uses 2 taps that are summed with the data, then each error is extended by a factor of three. DQPSK errors can be spaced the same as the tap spacing, so they can be canceled in the descrambler. In this case, two wrongs do make a right, so the observed errors can be in groups of 4 instead of 6. If a single error is made the whole packet is discarded, so the error extension property has no effect on the packet error rate. T0 + 1 SYMBOL CORRELATOR CORRELATION PEAK T0 + 2 SYMBOLS T0 CORRELATOR OUTPUT IS THE RESULT OF CORRELATING THE PN SEQUENCE WITH THE RECEIVED SIGNAL SAMPLES AT 2X CHIP RATE EARLY ON-TIME LATE OUTPUT REPEATS CORRELATION TIME FIGURE 13. CORRELATION PROCESS TABLE 10. DQPSK DATA DECODER PHASE SHIFT DIBIT PATTERN (D0, D1) D0 IS FIRST IN TIME 000 +90 01 +180 11 -90 10 HFA3860 |
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