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HFA3841CN Datasheet(PDF) 26 Page - Intersil Corporation |
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HFA3841CN Datasheet(HTML) 26 Page - Intersil Corporation |
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26 / 27 page  26 Master Clock Prescaler The HFA3841 contains a clock prescaler to provide flexibility in the choice of clock input frequencies. For 11Mb/s operation, the internal master clock, MCLK, must be between 11MHz and 16MHz. The clock generator itself requires an input from the prescaler that is twice the desired MCLK frequency. Thus the lowest oscillator frequency that can be used for an 11MHz MCLK is 22MHz. The prescaler can divide by integers and 1/2 steps (IE 1, 1.5, 2, 2.5). Another way to look at it is that the divisor ratio between the external clock source and the internal MCLK may be integers between 2 and 14. Typically, the 44MHz baseband clock is used as the input, and the prescaler is set to divide by 2. Another useful configuration is to set the prescaler to divide by 1.5 (resulting in 44MHz ÷3) for an MCLK of 14.67MHz. Off Chip If an off chip oscillator source is used, it should be connected to the XTALI pin. Insure that the signal amplitude meets CMOS levels at the XTALI pin. Oscillator The XTALI and XTALO pins provide an on-chip oscillator function to generate the master clock. For a standard pierce oscillator, the crystal is connected between XTALI and XTALO. Two capacitors, typically 15pF each, are connected from each pin to ground. The crystal should be a fundamental mode, specified under parallel resonance conditions. The load capacitance seen by the crystal will be approximately 2pF more than the series combination of C1 and C2 plus stray capacitance. After power on, the crystal will require time to stabilize before normal operation can commence. Insure that reset remains asserted for enough time for the crystal oscillator to stabilize. Power On Reset Configuration Power On Reset is issued to the HFA3841 with the HRESET pin or via the soft reset bit, SRESET, in the Configuration Option Register (COR, bit 7). HRESET originates from the HOST system which applies HRESET for at least 0.01ms after VCC has reached 90% of its end value (see PC-Card standard, Vol. 2, Ch. 4.12.1). The MD[15:8] pin values are sampled on the falling edge of HRESET or SRESET. These pins have internal 50K pull- down resistors. External pull-up resistors (typically 10k Ω) are used for bits that should be read as high at reset. The table below summarizes the effect per pin. MD[11], IDLE, has no equivalent functionality in any control register. When asserted at reset, it will inhibit firmware execution. This is used to allow the initial download of firmware in “Genesis Mode”. See the Hardware Reference Manual for more details. The latch is cleared when the Software Reset, SRESET, COR(7) is active. References For Intersil documents available on the internet, see web site http://www.intersil.com/ Intersil AnswerFAX (321) 724-7800. [1] IEEE Std 802.11-1999 Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specification. [2] HFA3860B Data Sheet, Direct Sequence Spread Spectrum Baseband Processor, Intersil Corporation, AnswerFAX Doc. No. 4594. [3] HFA3861 Data Sheet, Direct Sequence Spread Spectrum Baseband Processor, Intersil Corporation, AnswerFAX Doc. No. 4699. [4] HFA3783 Data Sheet, Quad IF, Intersil Corporation, AnswerFAX Doc. No. 4633. [5] HFA3683 Data Sheet, Direct Sequence Spread Spectrum Baseband Processor, Intersil Corporation, AnswerFAX Doc. No. 4634. [6] PC Card Standard 1996, PCMCIA/JEIDA. [7] AN9874 Application Note, Intersil Corporation, “ISA Plug and Play with the HFA3841”. [8] AN9844 Application Note, Intersil Corporation, “HFA3841 to PRISMII Connections”, AnswerFAX Doc. No. 99844 XTALI XTALO X1 C1 C2 FIGURE 25. POWER ON RESET CONFIGURATION TABLE 6. POR PINS AND FUNCTIONALITY PIN LATCH OUTPUT FUNCTIONALITY MD[8] Reserved MD[9] Nvdis Disable mapping of CS to NV (Flash) MD[10] MEM16 External memory (RAM and Flash) is 16 bits wide MD[11] IDLE See below MD[12] Reserved MD[15:13] MD15/14/13 FW purposes Preliminary - HFA3841 |
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