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HFA3841 Datasheet(PDF) 24 Page - Intersil Corporation

Part No. HFA3841
Description  Wireless LAN Medium Access Controller
Download  27 Pages
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HFA3841 Datasheet(HTML) 24 Page - Intersil Corporation

 
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24
Power Sequencing
The HFA3841 provides a number of firmware controlled port
pins that are used for controlling the power sequencing and
other functions in the front end components of the PHY.
Packet transmission requires precise control of the radio.
Ideally, energy at the antenna ceases after the last symbol of
information has been transmitted. Additionally, the
transmit/receive switch must be controlled properly to protect
the receiver. It's also important to apply appropriate
modulation to the PA while it's active.
Signaling sequences for the beginning and end of normal
transmissions are illustrated in Figure 24. Table 4 lists
applicable delays.
A transmission begins with PE2 as shown in Figure 24. Next,
the transmit/receive switch is configured for transmission via
the differential pair TR_SW and TR_SW_BAR. This is
followed by TX_PE which activates the transmit state
machine in the BBP. Lastly, PA_PE activates the PA. Delays
for these signals related to the initiation of transmission are
referenced to PE2.
Immediately after the final data bit has been clocked out of
the HFA3841, TX_PE is de-asserted. The HFA3841 then
waits for TXRDY to go inactive, signaling that the BBP has
modulated the final information-rich symbol. It then
immediately de-asserts PA_PE followed by placing the
transmit/receive switch in the receive position and ending
with PE2 going high. Delays for these signals related to the
termination of transmission are referenced to the rising edge
of PE2.
NOTE: Preamble/Header and Data is transmitted LSB first. TXD shown generated from rising edge of TXC.
FIGURE 22. BBP TRANSMIT PORT TIMING
TXC
TX_PE
TXD
TXRDY
FIRST DATA BIT SAMPLED
LSB
MSB
DATA PACKET
LAST DATA BIT SAMPLED
DEASSERTED WHEN LAST
CHIP OF MPDU CLEARS
MOD PATH OF 3861
FIGURE 23. BBP TRANSMIT PORT SIGNAL TIMING
tPEH
tTLP
tME
tRI
tTCD
tTCD
tRC
tTDH
tTDS
tDI
TX_PE
IOUT, QOUT
TXRDY
TXC
TXD
Preliminary - HFA3841


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