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HFA3841 Datasheet(PDF) 18 Page - Intersil Corporation

Part No. HFA3841
Description  Wireless LAN Medium Access Controller
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HFA3841 Datasheet(HTML) 18 Page - Intersil Corporation

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18
buffer access path) will result in the pre-read data
becoming invalidated.
• If another read cycle has invalidated the pre-read, then a
memory arbitration delay will occur on the next buffer
access path read cycle.
HIREQ-
Immediately after reset, the HIREQ- signal serves as the
RDY/BSY (per the PC Card standard). Once the HFA3841
firmware initialization procedure is complete, HIREQ- is
configured to operate as the interrupt to the PC Card socket
controller. Both Level Mode and Pulse Mode interrupts are
supported. By default, Level mode interrupts are used, so
the interrupt source must be specifically acknowledged or
disabled before the interrupt will be removed.
HRESET
When reset is removed, the CIS table is initialized and, once
complete, HIREQ- is set high (HIREQ- acts as RDY/BSY
from reset and is set high to indicate the card is ready for
use). The CIS table resides in Flash memory and is copied
to RAM during firmware initialization. The host system can
then initialize the card by reading the CIS information and
writing to the configuration register.
ISA PnP
The HFA3841 can be connected to the ISA bus and operate
in a Plug and Play environment with an additional chip such
as the Fujitsu MB86703, Texas Instruments TL16PNP200A,
or Fairchild Semiconductor NM95MS15. See the Application
Note AN9874, "ISA Plug and Play with the HFA3841" for
more details.
Register Interface
The logical view of the HFA3841 from the host is a block of
32 word wide registers. These appear in IO space starting at
the base address determined by the socket controller. There
are three types of registers.
HARDWARE REGISTERS (HW)
• 1 to 1 correspondence between addresses and registers.
• No memory arbitration delay, data transfer directly to/from
registers.
• AUX base and offset are write-only, to set up access
through AUX data port.
• Note: All register cycles, including hardware registers,
incur a short wait state on the PC Card bus to insure the
host cycle is synchronized with the HFA3841's internal
MCLK.
MEMORY MAPPED REGISTERS IN DATA RAM (MM)
• 1 to 1 correspondence.
• Requires memory arbitration, since registers are actually
locations in HFA3841 memory.
• Attribute memory access is mapped into RAM as Base-
address + 0x400.
• AUX port provides host access to any location in HFA3841
RAM (reserved).
BUFFER ACCESS PATH (BAP)
• No 1 to 1 correspondence between register address and
memory address (due to indirect access through buffer
address pointer registers).
• Auto increment of pointer registers after each access.
• Require memory arbitration since buffers are located in
HFA3841 memory.
• Buffer access may incur additional delay for Hardware
Buffer Chaining.
I/O OFFSET
NAME
TYPE
00
Command
MM
02
Param0
MM
04
Param1
MM
06
Param2
MM
08
Status
MM
0A
Resp0
MM
0C
Resp1
MM
0E
Resp2
MM
10
InfoFID
MM
20
RxFID
MM
22
AllocFID
MM
24
TxComplFID
MM
18
BAP Select0
MM
1C
BAP Offset0
MM
36
BAP Data0
BAP
1A
BAP Select1
MM
1E
BAP Offset1
MM
38
BAP Data1
BAP
30
EvStat
HW
32
IntEn
HW
34
EvAck
HW
14
Control
MM
28
SwSupport0
MM
2A
SwSupport1
MM
2C
SwSupport2
MM
3A
AuxBase
HW
3C
AuxOffset
HW
3E
AuxData
(reserved)
Preliminary - HFA3841


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