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HFA3841 Datasheet(PDF) 11 Page - Intersil Corporation

Part No. HFA3841
Description  Wireless LAN Medium Access Controller
Download  27 Pages
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HFA3841 Datasheet(HTML) 11 Page - Intersil Corporation

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11
NOTES:
11. 14.67MHz requires an odd divisor in the prescaler. Note that both edges of OSC are used to create MCLK and QCLK, thus a deviation from
50% duty cycle in OSC will result in corresponding changes in MBUS timing.
12. Timing delays between OSC and internal clocks are shown for information purposes only.
FIGURE 3. MBUS MEMORY TIMING - 14.67MHz MCLK
FIGURE 4.
Waveforms (Continued)
OSC
44MHz
23ns
10ns
14.67MHz
68.2ns
10ns
10ns
17ns
11.5ns
17ns
24ns
tH≥0
16ns
13ns
tH≥0
20ns
MBUS READ CYCLE
MBUS WRITE CYCLE
MCLK
(INTERNAL)
MCLKOUT
ADDRESS,
RAMCS_
MOE_
MD0-15
READ DATA
MWEH/L_
MD0-15
WRITE DATA
VALID DATA
VALID DATA AT MDIN
QCLK
(INTERNAL)
(NOTE 12)
(NOTE 12)
(NOTE 12)
MCLK
EMA [15:0]
EMCSxN
EMOEN
EMWRN
EMD [15:0]
tD1
tS1
tH1
tD1
tD2
tD3
tD4
tD5
tD6
Preliminary - HFA3841


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