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HFA3841 Datasheet(PDF) 9 Page - Intersil Corporation

Part No. HFA3841
Description  Wireless LAN Medium Access Controller
Download  27 Pages
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HFA3841 Datasheet(HTML) 9 Page - Intersil Corporation

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9
SIOIS16N Delay Falling from Address
tDFIOIS16
-
-
35
ns
SIOIS16N Delay Rising from Address
tDRIOIS16
-
-
35
ns
SWAITN Delay Falling from IOWRN
tDFWT
-
-
35
ns
SWAITN Width Time
tWWT
-
-
12,000
ns
SIOWRN High from SWAITN High
tDRIOWR
0-
-
ns
RADIO TX DATA - TX PATH
TXC Rising to TXD
tDTXD
-
-
10
ns
TXC Period
tTXC
4* tTMCK
--
ns
TXC Width Hi
tCHM
31
-
-
ns
TXC Width Lo
tCLM
31
-
-
ns
MCLK Period
ttMCK
22.7
-
-
ns
TXC Rising to TX_PE2 Deassert (See Note 9)
tDTX_PE2
-
TBD
TBD
ns
TX_RDY Assert Before TXC Rising
tTX_RDY
10
-
-
ns
TX_RDY Hold After TXC Rising (See Note 2)
tTX_RDYH
0-
-
RADIO RX DATA - RX PATH
RX_RDY Setup Time to RXC Positive Edge (See Note 3)
tSURX_RDY
10
-
-
ns
RX_RDY Hold Time from RXC Positive Edge (See Note 4)
tHRX_RDY
45
-
-
ns
RX_PE2 Delay from RX_RDY deAssert (See Note 8)
tDRX_PE2
-
3 * tMCLK
-ns
RX_PE2 Low Pulse Width (See Note 7)
tWRX_PE2
-
4 * tMCLK
-ns
RXD Setup Time to RXC Positive Edge (See Note 5)
tSURXD
10
-
-
ns
RXD Hold Time from RXC Positive Edge (See Note 5)
tHRXD
0-
-
ns
RXC Period (See Note 9)
tRXC
-
3 * tMCLK
-ns
MCLK Period
tMCLK
22.7
-
-
ns
RXC Width Hi
tRCHM
31
-
-
ns
RXC Width Lo
tRCLM
31
-
-
ns
NOTES:
2. TX_RDY is and'd with TXC_ONE_SHOT to shift data in shift register. However, once the last data bit is put on TXD output pin no further shifting
of bits is required. In addition, TX_RDY remains asserted until TX_PE2 is de-asserted which occurs several MAC MCLK's after the last data bit
is shifted into the BBP TX_PORT. Therefore, 0ns hold time is required for this signal.
TX_RDY is used by the BBP to signal that the PLCP header and preamble have been generated and the MAC must provide the MPDU data.
TX_RDY will remain asserted until TX_PE2 is deasserted by the MAC.
TX_PE2 is async to the TX_PORT.
3. MD_RDY is and'd with RXC_ONE_SHOT (RXDAV) to shift data in shift register. RX_RDY is not required to be valid until 1 MCLK after RXC is
sampled high. Therefore, a negative setup time could be used. Since this is an unlikely scenario, we will leave it at a nominal 10ns setup time.
4. MD_RDY is and'd with RXC_ONE_SHOT (RXDAV) to shift data in shift register. Therefore, for the last data bit, the MD_RDY must be held active
until RXC_ONE_SHOT is sampled high by MAC's MCLK. However, it is assumed that BBP will be used in a mode that keeps RX_RDY
(MD_RDY) and RXC running until RX_PE2 is de-asserted. The MAC will stop processing data after the number of bits retrieved from the PLCP
header length field are received. THEREFORE, the RX_RDY hold time with respect to RXC does not matter. However, should the RX_RDY
signal be cleared when the last RXD bit is received the hold time w/r RXC must be honored.
5. RXC positive edge clocks a flop which stores the RXD for internal usage.
6. RXC period (and Hi/Lo times) must be long enough for flops clocked by MAC MCLK to see 1 RXC high and 1 RXC low. Since RXC can be async
to MAC MCLK it is assumed that 3 MCLK periods will suffice.
7. RX_PE inactive width at BBP is 3 BBP MCLK's. Since BBP MCLK and MAC MCLK can be async minimum should be 4 MAC MCLK's.
8. Not yet verified, but seems reasonable. When RX_RDY drops before expected number of RXD bits is received, then Tx/Rx FSM in mpctl.v
signals timers which clear rx_pe2_int. More of a functional spec than a timing spec.
9. Need to sample 1 RXC high and 1 RXC low with MAC MCLK.
AC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Preliminary - HFA3841


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