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HFA3841 Datasheet(PDF) 6 Page - Intersil Corporation

Part No. HFA3841
Description  Wireless LAN Medium Access Controller
Download  27 Pages
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HFA3841 Datasheet(HTML) 6 Page - Intersil Corporation

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6
Special Hardware Functions for Port Pins
PJ0
SCK
MMI serial clock in or out
PJ1
SDO/SDIO
MMI serial data out or I/O
MOSI
SPI Master Out/Slave In
Also for MicroWire
PJ2
SDI/MISO
MMI serial data in
Or SPI Master In/Slave Out
SDDIR
MMI (SDIO) data direction
Low while SDIO is driven as an output
PJ3
SDE0
MMI serial device enable 0
Generally selects PHY controller
PCS-
SPI/MMI transfer qualifier
Asserted by hardware during transfer
PHYCS-
PHY chip select (3-3.5MB)
For memory-mapped PHY controllers
PJ4
SDE1
MMI serial device enable 1
For serial EPROM, synthesizer, etc.
SDDQ
MMI data delivery qualifier
Low for data on SDIO, high for address
SS-
SPI slave select
In slave mode SCK is serial clock input
PJ5
MREQ-
MBUS request
PJ6
MGNT-
MBUS grant
LED2
LED 2 driver
(Directly from I/O port)
PJ7
LED1
LED 1 driver
(Directly from I/O port)
PK0
GPCK
GP serial port clock in or out
UHSIn
Async handshake in
Indicates external async Rx ready
PK1
GPDO
GP serial port data output
UTXD
Async transmit data
PK2
GPDI
GP serial port data input
URXD
Async receive data
PK3
GPDS0
GP device select 0
UHSOut
Async handshake out
Indicates GP port async Rx ready
PK4
GPDS1
GP device select 1
PK5
PDA
PHY (or MAC) data available
Qualifies RXD input to MAC controller
UWDET
Unique word detected
Output from MAC controller
PK6
MBUSY
Medium busy
CCA status (PHY-dependent source)
RATE0
Data Rate select 0
PK7
EDET
Energy (or modulation) detect
RATE1
Data Rate select 1
PL0
TXE
Transmitter enable
PL1
RXE
Receiver enable
Can drive “awake” LED
PHYSLP
PHY sleep
(Directly from I/O port)
PL2
PHYRES
PHY reset
(Directly from I/O port)
PL3
SLOT
Slot time reference (in or out)
ANTSEL
Antenna select
(Directly from I/O port)
PL4
MA19
MBUS address bit 19
For 1M byte SRAM
LED0
LED 0 driver
(Directly from I/O port)
PL5
MA20
MBUS address bit 20
For 2M byte SRAM
PL6
MA21
MBUS address bit 21
For 4M byte SRAM
PL7
TXR
Transmitter ready
Preliminary - HFA3841


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