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HFA3841 Datasheet(PDF) 5 Page - Intersil Corporation |
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HFA3841 Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 27 page  5 Power PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION VCC_CORE3 14, 25, 39, 53 3.3V Core Supply VCC_IO3 66, 83, 98. 124 3.3V I/O Supply VCC_IO5 105 5V Tolerance Supply VSS_CORE3 13, 24, 37 Core VSS VSS_IO3 42, 52, 67, 82, 97, 115 I/O VSS TRST- 62 CMOS Input Reserved - Must be tied low through 1K ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with “-” are active low. NOTE: Output pins typically drive to positive voltage rail less 0.1V. Hence with a supply of 2.7V the output will just meet 5V TTL signal levels at rated loads. Port Pin Uses for PRISM Application PIN NAME PRISM I USE PRISM II™ USE 20 RXC RXC - Receive clock RXC - Receive clock 19 RXD RXD - Receive data RXD - Receive data 18 TXC TXC - Transmit clock TXC - Transmit clock 17 TXD TXD - Transmit data TXD - Transmit data 31 PJ0 SCLK - Clock for the SD serial bus. SCLK - Clock for the SD serial bus. 30 PJ1 SD - Serial bi-directional data bus SD - Serial bi-directional data bus 32 PJ2 R/W - An input to the HFA3860A used to change the direction of the SD bus when reading or writing data on the SD bus. Not Used 29 PJ3 CS - A Chip select for the device to activate the se- rial control port. (active low) CS_BAR - Chip select for HFA3861 baseband (active low) 65 PJ4 Not Used PE1 - Power Enable 1 8 PJ5 SYNTH_LE - Latches a frame of 22 bits after it has been shifted by the SCLK into the synthesizer reg- isters. LE_IF - Load enable for HFA3783 Quad IF 7 PJ6 LED - Activity indicator LED - Activity indicator 9 PJ7 Not Used RADIO_PE - RF power enable 35 PK0 Not Used LE_RF - Load enable for HFA3983 RF chip 34 PK1 Not Used SYNTHCLK - Serial clock to front end chips 33 PK2 Not Used SYNTHDATA - Serial data to front end chips 63 PK3 TX_PE_RF - Power Enable PA_PE - Transmit PA power enable 64 PK4 RX_PE_RF - Power Enable PE2 - Power Enable 2 21 PK5 MD_RDY - Header data and data packet are ready to be transferred from Baseband on RXD MDREADY - Header data and data packet are ready to be transferred from Baseband on RXD 22 PK6 CCA - Signal that the channel is clear to transmit. CCA - Signal that the channel is clear to transmit. 23 PK7 RADIO_PE - Master power control for the RF section CAL_EN - Calibration mode enable 15 PL0 TX_PE and PA_PE - Transmit Enable to Baseband TX_PE - Transmit Enable to Baseband 27 PL1 RX_PE - Receive Enable to Baseband RX_PE - Receive Enable to Baseband 26 PL2 RESET - Reset to Baseband RESET_BB - Reset Baseband 28 PL3 Not Used T/R-SW_BAR - Transient/Receive Control (Inverted) 43 PL4 MA19 (if required) MA19 (if required) 12 PL5 MA20 (if required) MA20 (if required) 11 PL6 MA21 (if required) Reserved 93 PL7 TX_RDY - Baseband ready to receive data on TXD (not used by firmware) T/R_SW - Transmit/Receive Control Preliminary - HFA3841 |
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