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HFA1149 Datasheet(PDF) 6 Page - Intersil Corporation |
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HFA1149 Datasheet(HTML) 6 Page - Intersil Corporation |
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6 / 13 page  6 PC Board Layout The frequency response of this amplifier depends greatly on the care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10 µF) tantalum in parallel with a small value (0.1 µF) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. Care must also be taken to minimize the capacitance to ground seen by the amplifier’s inverting input (-IN). The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. Thus, it is recommended that the ground plane be removed under traces connected to -IN, and connections to -IN should be kept as short as possible. Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth. By decreasing RS as CL increases, the maximum bandwidth is obtained without sacrificing stability. In spite of this, bandwidth still decreases as the load capacitance increases. Evaluation Board The performance of the HFA1149 may be evaluated using the HFA11XX Evaluation Board (part number HFA11XXEVAL). Please contact your local sales office for information. When evaluating this amplifier, the two 510 Ω gain setting resistors on the evaluation board should be changed to 250 Ω. The layout and schematic of the board are shown in Figure 2. NOTE: The SOIC version may be evaluated in the DIP board by using a SOIC-to-DIP adapter such as Aries Electronics Part Number 08-350000-10. . BOARD SCHEMATIC TOP LAYOUT BOTTOM LAYOUT FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT 1 2 3 4 8 7 6 5 +5V 10 µF 0.1 µF VH 50 Ω GND GND 510 Ω 510 Ω -5V 0.1 µF 10 µF 50 Ω IN OUT VL VH +IN VL V+ GND 1 V- OUT HFA1149 |
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