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HCTS540MS Datasheet(PDF) 1 Page - Intersil Corporation

Part No. HCTS540MS
Description  Radiation Hardened Inverting Octal Buffer/Line Driver, Three-State
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HCTS540MS Datasheet(HTML) 1 Page - Intersil Corporation

 
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCTS540DMSR
-55oC to +125oC
Intersil Class S Equivalent
20 Lead SBDIP
HCTS540KMSR
-55oC to +125oC
Intersil Class S Equivalent
20 Lead Ceramic Flatpack
HCTS540D/Sample
+25oC
Sample
20 Lead SBDIP
HCTS540K/Sample
+25oC
Sample
20 Lead Ceramic Flatpack
HCTS540HMSR
+25oC
Die
Die
HCTS540MS
Radiation Hardened
Inverting Octal Buffer/Line Driver, Three-State
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20, LEAD FINISH C
TOP VIEW
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F20, LEAD FINISH C
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE1
A0
A1
A2
A3
A4
A6
A5
A7
GND
VCC
Y0
Y1
Y2
OE2
Y3
Y4
Y5
Y6
Y7
OE1
A0
A1
A2
A3
A4
A6
A5
A7
GND
VCC
Y0
Y1
Y2
OE2
Y3
Y4
Y5
Y6
Y7
2
3
4
5
6
7
8
120
19
18
17
16
15
14
13
9
10
12
11
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
- Bus Driver Outputs 15 LSTTL Loads
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii
≤ 5µA at VOL, VOH
Description
The Intersil HCTS540MS is a Radiation Hardened inverting
Octal Buffer/Line Driver, with two active-low output enables.
The output enable pins (OE1 and OE2) control the three-
state outputs. If either enable is high the outputs will be in
the high impedance state. For data output both enables
(OE1 and OE2) must be low.
The HCTS540MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS540MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
September 1995
Spec Number
518631
File Number
2232.2


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