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HCTS373D Datasheet(PDF) 1 Page - Intersil Corporation |
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HCTS373D Datasheet(HTML) 1 Page - Intersil Corporation |
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1 / 11 page  638 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE HCTS373DMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead SBDIP HCTS373KMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead Ceramic Flatpack HCTS373D/Sample +25oC Sample 20 Lead SBDIP HCTS373K/Sample +25oC Sample 20 Lead Ceramic Flatpack HCTS373HMSR +25oC Die Die HCTS373MS Radiation Hardened Octal Transparent Latch, Three-State Pinouts 20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T20 TOP VIEW 20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F20 TOP VIEW 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 OE Q0 D0 D1 Q1 Q2 D3 D2 Q3 GND VCC D7 D6 Q6 Q7 Q5 D5 D4 Q4 LE 2 3 4 5 6 7 8 120 19 18 17 16 15 14 13 OE Q0 D0 D1 Q1 Q2 D2 D3 9 10 12 11 Q3 GND VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE Features • 3 Micron Radiation Hardened CMOS SOS • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit- Day (Typ) • Dose Rate Survivability: >1 x 1012 RAD (Si)/s • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Fanout (Over Temperature Range) - Bus Driver Outputs - 15 LSTTL Loads • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • LSTTL Input Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min • Input Current Levels Ii ≤ 5µA at VOL, VOH Description The Intersil HCTS373MS is a Radiation Hardened octal transpar- ent three-state latch with an active-low output enable. The out- puts are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable (OE) controls the three-state outputs. When the Output Enable (OE) is HIGH, the outputs are in the high impedance state. The latch operation is independent of the state of the Output Enable. The HCTS373MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS373MS is supplied in a 20 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). August 1995 Spec Number 518636 File Number 2131.2 |
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