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CDP68HC68T1D Datasheet(PDF) 10 Page - Intersil Corporation |
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CDP68HC68T1D Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 24 page 10 VSYS This input is connected to the system voltage. After the CPU initiates power down by setting bit 6 in the Interrupt Control Register to “1”, the level on this pin will terminate power down if it rises about 0.7V above the level at the VBATT input pin after previously falling below VBATT +0.7V. When power down is terminated, the PSE pin will return high and the Clock Output will be enabled. The CPUR output pin will also return high. The logic level present at this pin at the end of POR determines the CDP68HC68T1’s operating mode. VBATT The oscillator power source. The positive terminal of the bat- tery should be connected to this pin. When the level on the VSYS pin falls below VBATT +0.7V, the VBATT pin will be internally connected to the VDD pin. When the voltage on VSYS rises a threshold above (0.7V) the voltage on VBATT, the connection from VBATT to the VDD pin is opened. When the “LINE” input is used as the frequency source, VBATT may be tied to VDD or VSS. The “XTAL IN” pin must be at VSS if VBATT is at VSS. If VBATT is connected to VDD, the “XTAL IN” pin can be tied to VSS or VDD. XTAL IN, XTAL OUT These pins are connected to a 32,768Hz. 1.048576MHz, 2.097152MHz or 4.194304MHz crystal. If an external clock is used, it should be connected to “XTAL IN” with ‘XTAL OUT” left open. VDD The positive power-supply pin. Clock Control Register START-STOP A high written into this bit will enable the counter stages of the clock circuitry. A low will hold all bits reset in the divider chain from 32Hz to 1Hz. A clock out selected by bits 0, 1 and 2 will not be affected by the stop function except the 1Hz and 2Hz outputs. LlNE-XTAL When this bit is set high, clock operation will use the 50 or 60-cycle input present at the LINE input pin. When the bit is low, the crystal input will generate the 1Hz time update. XTAL Select One of 4 possible crystals is selected by value in these two bits: 0 = 4.194304MHz 2 = 1.048576MHz 1 = 2.097152MHz 3 = 32,768Hz 50-60Hz 50Hz is selected as the line input frequency when this bit is set high. A low will select 60Hz. The power-sense bit in the Interrupt Control Register must be set low for line frequency operation. Clock Out The three bits specify one of the 7 frequencies to be used as the squarewave clock output: 0 = XTAL 4 = Disable (low output) 1 = XTAL/2 5 = 1Hz 2 = XTAL/4 6 = 2Hz 3 = XTAL/8 7 = 50Hz or 60Hz XTAL Operation = 64Hz All bits are reset by a power-on reset. Therefore, the XTAL is selected as the clock output at this time. Interrupt Control Register Watchdog When this bit is set high, the watchdog operation will be enabled. This function requires the CPU to toggle the CE pin periodically without a serial-transfer requirement. In the event this does not occur, a CPU reset will be issued. Status Register must be read before re-enabling watchdog. Power Down A high in this location will initiate a power down. A CPU reset will occur, the CLK OUT and PSE output pins will be set low and the serial interface will be disabled. XTAL IN 22M T1 XTAL OUT C2 10 - 40pF C1 5 - 30pF NOTES: 7. All frequencies recommended oscillator circuit. C1, C2 values crystal dependent. 8. R used for 32KHz operation only. 100K - 300K range as specified by crystal manufacturer. FIGURE 7. OSCILLATOR CIRCUIT CLOCK CONTROL REGISTER (Write/Read) - Address 31H D7 D6 D5 D4 D3 D2 D1 D0 START LINE XTAL XTAL 50Hz CLK OUT CLK OUT CLK OUT SEL SEL STOP XTAL 1 0 60Hz 2 1 0 CDP68HC68T1 |
Similar Part No. - CDP68HC68T1D |
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Similar Description - CDP68HC68T1D |
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