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CDP1882C Datasheet(PDF) 1 Page - Intersil Corporation |
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CDP1882C Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 8 page 4-1 CDP1881C, CDP1882, CDP1882C CMOS 6-Bit Latch and Decoder Memory Interfaces Features • Performs Memory Address Latch and Decoder Functions Multiplexed or Non-Multiplexed • Decodes Up to 16K Bytes of Memory • Interfaces Directly with CDP1800-Series Microproces- sors at Maximum Clock Frequency • Can Replace CDP1866 and CDP1867 (Upward Speed and Function Capability) Ordering Information Description The CDP1881C, CDP1882 and CDP1882C are CMOS 6-bit memory latch and decoder circuits intended for use in CDP1800 series microprocessor systems. They can inter- face directly with the multiplexed address bus of this system at maximum clock frequency, and up to four 4K x 8-bit mem- ories to provide a 16K byte memory system. With four 2K x 8-bit memories an 8K byte system can be decoded. The devices are also compatible with non-multiplexed address bus microprocessors. By connecting the clock input to VDD, the latches are in the data-following mode and the decoded outputs can be used in general purpose memory- system applications. The CDP1881C, CDP1882 and CDP1882C are intended for use with 2K or 4K byte RAMs and are identical except that in the CDP1882 MWR and MRD are excluded. The CDP1882 is functionally identical to the CDP1882C. It differs in that the CDP1882 has recommended operating voltage range of 4V to 10.5V and the C version has a recom- mended operating voltage range of 4V to 6.5V. The CDP1881C, CDP1882 and CDP1882C are supplied in 20 lead and 18 lead packages, respectively. The CDP1881C is supplied only in a dual-in-line plastic pack- age (E suffix). The CDP1882 is supplied in dual-in-line, hermetic side-brazed ceramic (D suffix) and in plastic (E suffix) packages. Pinouts CDP1881C (PDIP) TOP VIEW CDP1882, CDP1882C (PDIP, CERDIP) TOP VIEW PACKAGE 5V 10V TEMP. RANGE (oC) PKG. NO. PDIP CDP1881CE - -40 to +85 E20.3 PDIP CDP1882CE - -40 to +85 E18.3 PDIP Burn-In CDP1882CEX - -40 to +85 E18.3 SBDIP - CDP1882D -40 to +85 D18.3 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 CLOCK MA5 MA4 MA3 MA2 MA1 MRD MA0 MWR VSS VDD A9 A10 A11 A8 CS0 CS1 CS2 CS3 CE 10 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 1 VDD A9 A10 A11 CS0 CS1 CS2 A8 CS3 CLOCK MA5 MA4 MA3 MA2 MA1 CE MA0 VSS File Number 1367.2 March 1997 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 |
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