4-73

and read by the CPU, at which time the next key pressed in

the scanning order is detected. If the first key remains closed

after the CPU reads the data and resets the DA output, on

the low-to-high transition of TPB, an auxiliary signal (RPT) is

generated and is available to the CPU to indicate an auto-

repeat condition. The RPT output is reset high at the end of

the debounce delay after the depressed key is released.

The DEBOUNCE input provides a terminal connection for an

external user-selected RC circuit to eliminate false detection

of a keydown condition caused by keyboard noise. The oper-

ation of the DEBOUNCE circuit is shown in Figure 2 (Pin

36). When a valid keydown is detected, the on-chip active-

inverter, which clocks the DA flip-flop (latching the DA output

low and inhibiting the scan clock). (The DA F/F is reset by

the low-to-high transition of TPB when the CS inputs are

enabled). When a valid key-release is detected RN is dis-

charge time is again sensed by the Schmitt-trigger inverter,

enabling the scan clock to continue on the next high-to-low

transitions of TPB, after the current keycode data is read by

the CPU.

PARAMETER

(V)

LIMITS

UNITS

CDP1871AD, CDP1871AE

CDP1871ACD, CDP1871ACE

MIN

(NOTE 1)

TYP

MAX

MIN

(NOTE 1)

TYP

MAX

Clock Cycle Time

5

-

-

-

-

-

-

Note 2

10

-

-

-

-

-

-

Note 2

Clock Pulse Width High

5

100

40

-

100

40

-

ns

10

50

20

-

-

-

-

ns

Data Available Valid Delay

5

-

260

500

-

260

500

ns

10

-

130

250

-

-

-

ns

Data Available Invalid Delay

5

-

70

150

-

70

150

ns

10

-

35

75

-

-

-

ns

Scan Count Delay

(Non-Repeat)

5

-

850

1900

-

850

1900

ns

10

-

425

950

-

-

-

ns

Data Out Valid Delay

5

-

120

250

-

120

250

ns

10

-

60

125

-

-

-

ns

Data Out Hold Time

5

-

100

200

-

100

200

ns

10

-

50

100

-

-

-

ns

Repeat Valid Delay

5

-

150

400

-

150

400

ns

10

-

75

200

-

-

-

ns

Repeat Invalid Delay

5

-

350

700

-

350

700

ns

10

-

170

350

-

-

-

ns

NOTES:

k = 0.9ns per pF

c = Keyboard capacitance (pF)

CDP1871A, CDP1871AC