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CDP1854AC Datasheet(PDF) 8 Page - Intersil Corporation |
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CDP1854AC Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 21 page 5-49 Description of Mode 1 Operation CDP1800-Series Microprocessor Compatible (Mode Input = VDD) Initialization and Controls In the CDP1800-series microprocessor compatible mode, the CDP1854A is configured to receive commands and send status via the microprocessor data bus. The register connected to the transmitter bus or the receiver bus is determined by the RD/WR and RSEL inputs as follows: In this mode the CDP1854A is compatible with a bidirectional bus system. The receiver and transmitter buses are connected to the bus. CDP1800-series microprocessor I/O control output signals can be connected directly to the CDP1854A inputs as shown in Figure 2. The CLEAR input is pulsed, resetting the Control, Status, and Receiver Holding Registers and setting SERIAL DATA OUT (SDO) high. The Control Register is loaded from the Transmitter Bus in order to determine the operating configuration for the UART. Data is transferred from the Transmitter Bus inputs to the Control Register during TPB when the UART is selected (CS1 • CS2 • CS3 = 1) and the Control Register is designated (RSEL = H, RD/WR = L). The CDP1854A also has a Status Register which can be read onto the Receiver Bus (R BUS 0 - R BUS 7) in order to determine the status of the UART. Some of these status bits are also available at separate terminals as indicated in Table 2. Transmitter Operation Before beginning to transmit, the TRANSMlT REQUEST (TR) bit in the Control Register (see bit assignment, Table 4) is set. Loading the Control Register with TR = 1 (bit 7 = high) inhibits changing the other control bits. Therefore two loads are required: one to format the UART, the second to set TR. When TR has been set, a TRANSMlTTER HOLDING REG- ISTER EMPTY (THRE) interrupt will occur, signalling the microprocessor that the Transmitter Holding Register is empty and may be loaded. Setting TR also causes assertion of a low-level on the REQUEST TO SEND (RTS) output to the peripheral. It is not necessary to set TR for proper opera- tion for the UART. If desired, it can be used to enable THRE interrupts and to generate the RTS signal. The Transmitter Holding Register is loaded from the bus by TPB during exe- cution of an output instruction. The CDP1854A is selected by CS1 • CS2 • CS3 = 1, and the Holding Register is selected by RSEL = L and RD/WR = L. When the CLEAR TO SEND (CTS) input, which can be connected to a periph- eral device output, goes low, the Transmitter Shift Register will be loaded from the Transmitter Holding Register and data transmission will begin. If CTS is always low, the Trans- mitter Shift Register will be loaded on the first high-to-low edge of the clock which occurs at least 1/2 clock period after the trailing edge of TPB and transmission of a start bit will occur 1/2 clock period later (see Figure 3). Parity (if pro- grammed) and stop bit(s) will be transmitted following the last data bit. If the word length selected is less than 8 bits, the most significant unused bits in the transmitter shift regis- ter will not be transmitted. One transmitter clock period after the Transmitter Shift Reg- ister is loaded from the Transmitter Holding Register, the THRE signal will go low and an interrupt will occur (INT goes low). The next character to be transmitted can then be loaded into the Transmitter Holding Register for transmission with its start bit immediately following the last stop bit of the previous character. This cycle can be repeated until the last character is transmitted, at which time a final THRE • TSRE interrupt will occur. This interrupt signals the microprocessor that TR can be turned off. This is done by reloading the orig- inal control byte in the Control Register with the TR bit 0, thus terminating the REQUEST TO SEND (RTS) signal. SERIAL DATA OUT (SDO) can be held low by setting the BREAK bit in the Control Register (see Table 4). SDO is held low until the BREAK bit is reset. Receiver Operation The receive operation begins when a start bit is detected at the SERlAL DATA IN (SDl) input. After detection of the first high-to-low transition on the SDl line, a valid start bit is verified by checking for a low-level input 7-1/2 receiver clock periods later. When a valid start bit has been verified, the fol- lowing data bits, parity bit (if programmed) and stop bit(s) are shifted into the Receiver Shift Register by clock pulse 7-1/2 TABLE 3. REGISTER SELECTION SUMMARY RSEL RD/WR FUNCTION Low Low Load Transmitter Holding Register from Transmitter Bus Low High Read Receiver Holding Register from Receiver Bus High Low Load Control Register from Transmitter Bus High High Read Status Register from Receiver Bus FIGURE 2. RECOMMENDED CDP1800-SERIES CONNECTION, MODE 1 (NON-INTERRUPT DRIVEN SYSTEM) N0 N1 N2 MRD TPB INT EFX EFX EFX EFX BUS CLEAR (8) CPU RSEL CS1 CS2 RD/WR TPB INT THRE DA T BUS CS3 T CLOCK R CLOCK RTS CTS ES PSI SDO SDI MODE CLEAR VDD FE PE/OE R BUS VSS VDD UART CDP1854A CDP1854A, CDP1854AC |
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Similar Description - CDP1854AC |
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