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CDP1823C Datasheet(PDF) 5 Page - Intersil Corporation |
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CDP1823C Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 6 page 6-35 Data Hold Time from MWR (Note 1) tDH 5 50 - 70 - ns Chip Select Setup tCS 5 210 - 300 - ns NOTES: 1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing. 2. Minimum timing to allow the indicated function to occur. Write Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF (Continued) PARAMETER SYMBOL VDD (V) LIMITS UNITS +25oC, -55oC +125oC (NOTE 2) MIN MAX (NOTE 2) MIN MAX ADDRESS tWC tAS tAH tCS tWW tDH VALID DATA CS1, CS4 CS2, CS3, CS5 MWR BUS 0-7 tDS NOTE: 1. MRD must be high during write operation. FIGURE 2. WRITE CYCLE TIMING WAVEFORMS Data Retention Specifications PARAMETER SYMBOL TEST CONDITIONS LIMITS UNITS VDR (V) VDD (V) +25oC, -55oC +125oC MIN MAX MIN MAX Minimum Data Retention Voltage (Note 1) VDR - - - 2 - 2.5 V Data Retention Quiescent Current IDD 2 - - 100 - 400 µA Chip Deselect to Data Retention Time tCDR - 5 450 - 650 - ns Recovery to Normal Operation Time tRC - 5 450 - 650 - ns NOTE: 1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing. CDP1823C/3 |
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Similar Description - CDP1823C |
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