CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.

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SEMICONDUCT OR

CD54AC163/3A

CD54ACT163/3A

Synchronous Presettable Binary Counters

Functional Diagram

ACT INPUT LOAD TABLE

INPUT

UNIT LOAD (NOTE 1)

Pn

0.13

CP

1

MR, TE

0.83

SPE

0.67

PE

0.5

NOTE:

1. Unit load is

∆I

SPE

CP

MR

PE

TE

9

2

1

7

10

GND = 8

3456

14

13

12

11

15

Q0

Q1

Q2

Q3

TC

P0

P1

P2

P3

June 1997

File Number

3893

Description

The CD54AC163/3A and CD54ACT163/3A are synchronous

presettable binary counters that utilize the Harris Advanced

CMOS

Logic

technology.

The

CD54AC163/3A

and

CD54ACT163/3A are reset synchronously with the clock.

Counting and parallel presetting are both accomplished syn-

chronously with the negative-to-positive transition of the

clock.

A LOW level on the Synchronous Parallel Enable input, SPE,

disables the counting operation and allows data at the P0 to

P3 inputs to be loaded into the counter (provided that the

setup and hold requirements for SPE are met).

The counters are reset with a LOW level on the Master

Reset input, MR. The requirements for setup and hold time

with respect to the clock must be met.

Two count enables, PE and TE, in each counter are provided

for n-bit cascading. Reset action occurs regardless of the

level of the SPE, PE and TE inputs.

The look-ahead carry feature simplifies serial cascading of

the counters. Both count enable inputs (PE and TE) must be

HIGH to count. The TE input is gated with the Q outputs of

all four stages so that at the maximum count, the terminal

count (TC) output goes HIGH for one clock period. This TC

pulse is used to enable the next cascaded stage.

The CD54AC163/3A and CD54ACT163/3A are supplied in

16 lead dual-in-line ceramic packages (F suffix).

Absolute Maximum Ratings

For Up to 4 Outputs Per Device, Add

±25mA For Each

Additional Output

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±100mA

Lead Temperature (During Soldering)

At Distance 1/16in.

± 1/32in. (1.59mm ± 0.79mm)

Unit Inserted Into a PC Board (Min Thickness 1/16in., 1.59mm)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Recommended Operating Conditions

Unless Otherwise Specified, All Voltages Referenced to GND

CD54AC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

CD54ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

Input Rise and Fall Slew Rate, dt/dv

at 1.5V to 3V (AC Types) . . . . . . . . . . . . . . . . . . . 0ns/V to 50ns/V

at 3.6V to 5.5V (AC Types) . . . . . . . . . . . . . . . . . 0ns/V to 20ns/V

at 4.5V to 5.5V (AC Types) . . . . . . . . . . . . . . . . . 0ns/V to 10ns/V

COMING SOON!

COMPLETE DATA SHEET