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CD4502BMS Datasheet(PDF) 6 Page - Intersil Corporation

Part # CD4502BMS
Description  CMOS Strobed Hex Inverter/Buffer
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD4502BMS Datasheet(HTML) 6 Page - Intersil Corporation

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Specifications CD4502BMS
Test Circuit and Waveform
FIGURE 2. DISABLE DELAY TIMES TEST CIRCUIT AND WAVEFORMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
OPEN
GROUND
VDD
9V
± -0.5V
OSCILLATOR
50kHz
25kHz
Static Burn-In 1
Note 1
2, 5, 7, 9, 11, 14
1, 3, 4, 6, 8, 10, 12,
13, 15
16
Static Burn-In 2
Note 1
2, 5, 7, 9, 11, 14
8
1, 3, 4, 6, 10, 12,
13, 15, 16
Dynamic Burn-
In Note 1
-
8
16
2, 5, 7, 9, 11, 14
4
1, 3, 6, 10, 12, 13,
15
Irradiation
Note 2
2, 5, 7, 9, 11, 14
8
1, 3, 4, 6, 10, 12,
13, 15, 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K
± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K
± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V
± 0.5V
Logic Diagram
FIGURE 1. LOGIC DIAGRAM OF 1 OF 6 IDENTICAL INVERTER/BUFFERS
VDD
VSS
Q1
DI *
*
*
3-STATE
OUTPUT
DISABLE
INHIBIT
INVERTER/BUFFER NO. 1
VDD
VSS
TO 5 OTHER
INVERTER/BUFFERS
* ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
TRUTH TABLE
DISABLE
INHIBIT
Dn
Qn
00
0
1
00
1
0
01
X
0
1X
X
Z
Logic 0 = Low
Logic 1 = High
Z = High Impedance
X = Don’t Care
14
15
16
9
13
12
11
10
1
2
3
5
7
6
8
D3
Q3
D1
Q1
D2
VSS
Q2
VDD
Q6
D5
INHIBIT
Q5
D4
Q4
D6
DISABLE
4
PULSE
GENERATOR
A
CL
1k
0.01k
µF
VDD
TEST CONDITIONS
TEST
PIN 15
POINT A
tPHZ
VSS
VSS
tPLZ
VDD
VDD
tPZL
VDD
VDD
tPZH
VSS
VSS
50%
tPLZ
tPHZ
10%
90%
tPZL
tPZH
VDD
VOL
VOH
VSS
50%
10%
90%


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