10

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

CD4067BMS, CD4097BMS

Chip Dimensions and Pad Layouts

CD4067BMSH

CD4097BMSH

Dimensions in parentheses are in millimeters

and are derived from the basic inch dimensions

Special Considerations

In applications where separate power sources are used to

drive VDD and the signal inputs, the VDD current capability

should exceed VDD/RL (RL = effective external load). This

provision avoids permanent current flow or clamp action on

the VDD supply when power is applied or removed from the

CD4067BMS or CD4097BMS.

When switching from one address to another, some of the

ON periods of the channels of the multiplexers will overlap

momentarily, which may be objectionable in certain applica-

tions. Also when a channel is turned on or off by an address

input, there is a momentary conductive path from the chan-

nel to VSS, which will dump some charge from any capacitor

connected to the input or output of the channel. The inhibit

input turning on a channel will similarly dump some charge

to VSS.

The amount of charge dumped is mostly a function of the

signal level above VSS. Typically, at VDD - VSS = 10V, a

100pF capacitor connected to the input or output of the

channel will lose 3 to 4% of its voltage at the moment the

channel turns on or off. This loss of voltage is essentially

independent of the address or inhibit signal transition time, if

the transition time is less than 1 - 2

µs. When the inhibit sig-

nal turns a channel off, there is no charge dumping to VSS.

Rather, there is a slight rise in the channel voltage level

(65mV typ.) due to capacitive coupling from inhibit input to

channel input or output. Address inputs also couple some

voltage steps onto the channel signal levels.

In certain applications, the external load resistor current may

include both VDD and signal-line components. To avoid

drawing VDD current when switch current flows into the

transmission gate inputs, the voltage drop across the bidi-

rectional switch must not exceed 0.8 volt (calculated from

RON values shown in ELECTRICAL CHARACTERISTICS

CHART - Table 1). no VDD current will flow through RL if the

switch current flows into terminal 1 on the CD4067BMS, ter-

minals 1 and 17 on the CD4097BMS.

METALLIZATION:

Thickness: 11k

Å

PASSIVATION:

10.4kÅ - 15.6k

BOND PADS:

0.004 inches X 0.004 inches MIN

DIE THICKNESS:

0.0198 inches - 0.0218 inches