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AD7891AS-1 Datasheet(PDF) 4 Page - Analog Devices |
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AD7891AS-1 Datasheet(HTML) 4 Page - Analog Devices |
4 / 20 page AD7891 –4– REV. D TIMING CHARACTERISTICS1, 2 Parameter A, B, Y Versions Unit Test Conditions/Comments tCONV 1.6 ms max Conversion Time Parallel Interface t1 0 ns min CS to RD/WR Setup Time t2 35 ns min Write Pulse Width t3 25 ns min Data Valid to Write Setup Time t4 5 ns min Data Valid to Write Hold Time t5 0 ns min CS to RD/WR Hold Time t6 35 ns min CONVST Pulse Width t7 55 ns min EOC Pulse Width t8 35 ns min Read Pulse Width t9 3 25 ns min Data Access Time after Falling Edge of RD t10 4 5 ns min Bus Relinquish Time after Rising Edge of RD 30 ns max Serial Interface t11 30 ns min RFS Low to SCLK Falling Edge Setup Time t12 3 20 ns max RFS Low to Data Valid Delay t13 25 ns min SCLK High Pulse Width t14 25 ns min SCLK Low Pulse Width t15 3 5 ns min SCLK Rising Edge to Data Valid Hold Time t16 3 15 ns max SCLK Rising Edge to Data Valid Delay t17 20 ns min RFS to SCLK Falling Edge Hold Time t18 4 0 ns min Bus Relinquish Time after Rising Edge of RFS 30 ns max t18A 4 0 ns min Bus Relinquish Time after Rising Edge of SCLK 30 ns max t19 20 ns min TFS Low to SCLK Falling Edge Setup Time t20 15 ns min Data Valid to SCLK Falling Edge Setup Time t21 10 ns min Data Valid to SCLK Falling Edge Hold Time t22 30 ns min TFS Low to SCLK Falling Edge Hold Time NOTES 1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 2, 3, and 4. 3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice. 1.6mA 200 A 1.6V TO OUTPUT PIN 50pF Figure 1. Load Circuit for Access Time and Bus Relinquish Time |
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