7-832

Specifications CD4033BMS

Static Burn-In 1

Note 1

4 - 7, 9 - 13

1 - 3, 8, 14, 15

16

Static Burn-In 2

Note 1

4 - 7, 9 - 13

8

1 - 3, 14 - 16

Dynamic Burn-

In Note 1

-

2, 3, 8, 14, 15

16

4 - 7, 9 - 13

1

Irradiation

Note 2

4 - 7, 9 - 13

8

1 - 3, 14 - 16

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K

± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K

± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD

= 10V

± 0.5V

Timing Diagram

FIGURE 2. CD4033BMS TIMING DIAGRAM

FIGURE 3. DETAIL OF TYPICAL FLIP-FLOP STAGE

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

FUNCTION

OPEN

GROUND

VDD

9V

± -0.5V

OSCILLATOR

50kHz

25kHz

0 1

234 5 6 7 8 9

0 1

8

4 5 6 7 8 9

1 2

CLOCK

RESET

CLOCK

INHIBIT

LAMP

TEST

RBI

COUT

(CLOCK

÷ 10)

a

b

c

d

e

f

g

RBO

p

n

CL

CL

p

n

CL

CL

p

n

CL

CL

p

n

CL

CL

CL

CL

CL

Q

R

D

Q

D

CL

R

Q

Q

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