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CD4019BMS Datasheet(PDF) 1 Page - Intersil Corporation

Part No. CD4019BMS
Description  CMOS Quad AND/OR Select Gate
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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CD4019BMS Datasheet(HTML) 1 Page - Intersil Corporation

   
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4019BMS
CMOS Quad AND/OR Select Gate
Pinout
CD4019BMS
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
B4
A3
B3
A2
B2
A1
VSS
B1
VDD
Kb
D4 = A4 Ka + B4 Kb
D3 = A3 Ka + B3 Kb
D2 = A2 Ka + B2 Kb
D1 = A1 Ka + B1 Kb
Ka
A4
14
916
VDD
VSS
11
10
12
1
15
D3
D2
D1
8
2
13
D4
A4
3
4
5
6
7
B4
A3
B3
A2
B2
A1
B1
D4 = (A4 Ka) + (B4 Kb)
Ka Kb
Features
• High Voltage Type (20V Rating)
• Medium Speed Operation tPHL = tPLH = 60ns (typ.) at
CL = 50pF, VDD = 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
• Maximum Input Current of 1
µa at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Applications
• And/Or Select Gating
• Shift-Right/Shift-Left Registers
• True/Complement Selection
• AND/OR/Exclusive-OR Selection
Description
CD4019BMS types consist of four AND/OR select gate con-
figurations, each consisting of two 2-input AND gates driving
a single 2-input OR gate. Selection is accomplished by con-
trol bits Ka and Kb. In addition to selection of either channel
A or channel B information, the control bits can be applied
simultaneously to accomplish the logical A + B function.
The CD4019BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP
H4T
Frit Seal DIP
H1E
Ceramic Flatpack
H3X
November 1994
File Number
3299


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