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AD7790 Datasheet(PDF) 1 Page - Analog Devices

Part No. AD7790
Description  Low Power, 16-Bit Buffered Sigma-Delta ADC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7790 Datasheet(HTML) 1 Page - Analog Devices

 
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Low Power, 16-Bit
Buffered Sigma-Delta ADC
Data Sheet
AD7790
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no re-
sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2004–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
Power
Supply: 2.5 V to 5.25 V operation
Normal: 75 μA maximum
Power-down: 1 μA maximum
RMS noise: 1.1 μV at 9.5 Hz update rate
16-bit p-p resolution
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator
Programmable gain amplifier
Rail-to-rail input buffer
VDD monitor channel
Temperature range: –40°C to +105°C
10-lead MSOP
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops
FUNCTIONAL BLOCK DIAGRAM
03538-0-001
SERIAL
INTERFACE
INTERNAL
CLOCK
16-BIT
ADC
AIN
GND
REFIN
AD7790
VDD
DIGITAL
PGA
BUF
VDD
GND
Figure 1.
GENERAL DESCRIPTION
The AD7790 is a low power, complete analog front end for
low frequency measurement applications. It contains a low
noise 16-bit ∑-Δ ADC with one differential input that can be
buffered or unbuffered along with a digital PGA, which allows
gains of 1, 2, 4, and 8.
The device operates from an internal clock. Therefore, the user
does not have to supply a clock source to the device. The output
data rate from the part is software programmable and can be
varied from 9.5 Hz to 120 Hz, with the rms noise equal to
1.1 μV at the lower update rate. The internal clock frequency
can be divided by a factor of 2, 4, or 8, which leads to a reduc-
tion in the current consumption. The update rate, cutoff
frequency, and settling time will scale with the clock frequency.
The part operates with a power supply from 2.5 V to 5.25 V.
When operating from a 3 V supply, the power dissipation for
the part is 225 μW maximum. It is housed in a 10-lead MSOP.


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