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AD7790 Datasheet(PDF) 4 Page - Analog Devices

Part No. AD7790
Description  Low Power, 16-Bit Buffered Sigma-Delta ADC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7790 Datasheet(HTML) 4 Page - Analog Devices

 
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AD7790
Data Sheet
Rev. A | Page 4 of 20
SPECIFICATIONS (continued)1
Parameter
AD7790B
Unit
Test Conditions/Comments
REFERENCE INPUT (continued)
Normal Mode Rejection2
@ 50 Hz, 60 Hz
65
dB min
73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004
@ 50 Hz
80
dB min
90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014
@ 60 Hz
80
dB min
90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114
Common Mode Rejection
Input Range = ±2.5 V, AIN = 1 V
@ DC
100
dB typ
FS[2:0] = 1004
@ 50 Hz, 60 Hz
110
dB typ
50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114)
LOGIC INPUTS
All Inputs Except SCLK2
VINL, Input Low Voltage
0.8
V max
VDD = 5 V
0.4
V max
VDD = 3 V
VINH, Input High Voltage
2.0
V min
VDD = 3 V or 5 V
SCLK Only (Schmitt-Triggered Input)2
VT(+)
1.4/2
V min/V max
VDD = 5 V
VT(–)
0.8/1.4
V min/V max
VDD = 5 V
VT(+) – VT(–)
0.3/0.85
V min/V max
VDD = 5 V
VT(+)
0.9/2
V min/V max
VDD = 3 V
VT(–)
0.4/1.1
V min/V max
VDD = 3 V
VT(+) - VT(–)
0.3/0.85
V min/V max
VDD = 3 V
Input Currents
±1
µA max
VIN = VDD or GND
Input Capacitance
10
pF typ
All Digital Inputs
LOGIC OUTPUTS
VOH, Output High Voltage2
VDD – 0.6
V min
VDD = 3 V, ISOURCE = 100 µA
VOL, Output Low Voltage2
0.4
V max
VDD = 3 V, ISINK = 100 µA
VOH, Output High Voltage2
4
V min
VDD = 5 V, ISOURCE = 200 µA
VOL, Output Low Voltage2
0.4
V max
VDD = 5 V, ISINK = 1.6 mA
Floating-State Leakage Current
±1
µA max
Floating-State Output Capacitance
10
pF typ
Data Output Coding
Offset Binary
POWER REQUIREMENTS5
Power Supply Voltage
VDD – GND
2.5/5.25
V min/max
Power Supply Currents
IDD Current6
75
µA max
65 µA typ, VDD = 3.6 V, Unbuffered Mode
145
µA max
130 µA typ, VDD = 3.6 V, Buffered Mode
80
µA max
73 µA typ, VDD = 5.25 V, Unbuffered Mode
160
µA max
145 µA typ, VDD = 5.25 V, Buffered Mode
IDD (Power-Down Mode)
1
µA max
5
Digital inputs equal to VDD or GND.
6
The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 15).


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