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CA3277 Datasheet(PDF) 3 Page - Intersil Corporation

Part No. CA3277
Description  Dual 5V Regulator with Serial Data Buffer Interface for Microcontroller Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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CA3277 Datasheet(HTML) 3 Page - Intersil Corporation

   
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Specifications CA3277
DATA COMPARATOR
Data Comp Thd
VBATT
- 3.6
VBATT
-2.9
VBATT
-2.2
V
Data Comp Hysteresis
-
200
-
mV
DATA OUT Low
VOL
VBATT = 16V, VDATA IN = (VBATT -5V)
-
-
0.15
V
DATA OUT High
VOH
VBATT = 16V, VDATA IN = 16V
VOUT1
-0.15
-
5.25
V
DATA OUT Low Sink Current
IOL
VDATA IN Low
-
1
-
mA
DATA OUT High Source Current
IOH
VDATA IN High
-
-50
-
µA
IGNITION COMPARATOR
Ign Comp Thd
5.5
6
6.5
V
Ign Comp Hysteresis
-
200
-
mV
IGN OUT Low
VOL
-
-
0.15
V
IGN OUT High
VOH
4.6
5.25
V
IGN OUT Low Sink Current
IOL
VIGN IN Low
-
1
-
mA
IGN OUT High Source Current
IOH
VIGN IN High
-
-70
-
µA
OTHER PARAMETERS
Idle Current
IQ
VBATT = 12.6V, No Loads, VEN = VIGN IN = 0V
-
500
800
µA
Over-Voltage Shutdown
VBATT(OVSD)
Ramp VBATT Up Until OUT1 and OUT2 Shut-
down
19
20.5
23
V
Thermal Shutdown
TJ
-
150
-
oC
Ripple Rejection
1VPP at 3kHz on BATT INPUT, Measure AC
Ripple on OUT1, OUT2
45
55
-
dB
NOTES:
1. For negative voltages on the BATT and IGN IN inputs, current drain is primarily reverse junction leakage, except when DATA IN, CUR
OUT, ENABLE and RESET are directly connected to BATT. (Note 2)
2. For negative voltage DATA IN, CUR OUT, ENABLE and RESET interface to NPN or equivalent on-chip structures; providing a forward
junction for current conduction into the IC. Negative current must be limited by the impedance of the external connection. This is also the
case where these terminals are interconnected to BATT, Normal application does not require the BATT connection, except for DATA IN
where a series diode for reverse current blocking may be used. (see Description text information)
3. Refer to the Electrical Characteristic TABLE for all Self-Limiting values.
4. Dissipation, approximately equals: PD [(VINIIN) + (VCUR OUTICUR OUT) - 5(IOUT1+IOUT2)], where IINVIN is IGN IN and BATT input dissi-
pation and VOUT1~VOUT2~5V. This assumes neglibible dissipation for the Ignition Comp., Reset and Data Comp. Outputs.
5. Dropout Voltage is VDO1 = (VBATT -VOUT1) for REG. OUT1 and VDO2 = (VBATT -VOUT2) for REG. OUT2
6. Reset Delay Time, tRST is the time period that the RESET (Pin 8) is low following the discharge of the CRST capacitor to ground. For test
evaluation, the CRST pin may be discharged repetitively with a transistor switch. The RESET pin switches from low to high when the
CRST pin is charged to approximately 3V. Normal ATE testing measures the source charging current. which is typically 10
µA. For any
other value of Capacitor the charge time, t for reset is determined as follows: t
~308C, where C is in
µF and t is in milliseconds.
(i.e. C = 0.47
µF, t = 141ms)
Electrical Specifications TA = -40oC to +85oC, VBATT = 13.5V, ENABLE ON (VEN = 3.5V), IGN IN connected to BATT, OUT1 and
OUT2 bypassed with 20
µF to GND, DATA IN connected through 250Ω to BATT, LOADS: OUT1 = 50mA,
OUT2 = 80mA; Unless Otherwise Specified (Refer to Figure 4 Test Circuit) (Continued)
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS


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