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AD7707 Datasheet(PDF) 23 Page - Analog Devices

Part No. AD7707
Description  3-Channel 16-Bit, Sigma-Delta ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7707 Datasheet(HTML) 23 Page - Analog Devices

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AD7707
Rev. B | Page 23 of 52
CALIBRATION SEQUENCES
The AD7707 contains a number of calibration options as
previously outlined. Table 25 summarizes the calibration types,
the operations involved, and the duration of the operations.
There are two methods of determining the end of calibration.
The first is to monitor when DRDY returns low at the end of
the sequence. DRDY not only indicates when the sequence is
complete, but also that the part has a valid new sample in its
data register. This valid new sample is the result of a normal
conversion, which follows the calibration sequence. The second
method of determining when calibration is complete is to
monitor the MD1 and MD0 bits of the setup register. When
these bits return to 0 (0 following a calibration command), it
indicates that the calibration sequence is complete. This method
does not give any indication of there being a valid new result in
the data register. However, it gives an earlier indication than
DRDY that calibration is complete. The duration to when the
Mode Bits (MD1 and MD0) return to 00 represents the
duration of the calibration carried out). The sequence to when
DRDY goes low also includes a normal conversion and a
pipeline delay, tP, to correctly scale the results of this first
conversion. tP will never exceed 2000 × tCLKIN. The time for both
methods is given in the
.
Table 25
Table 25. Calibration Sequences
Calibration Type
MD1, MD0
Calibration Sequence
Duration to Mode Bits
Duration to DRDY
Self-Calibration
0, 1
Internal ZS calibration at selected gain +
6 × 1/output rate
9 × 1/output rate + tP
Internal FS calibration at selected gain
ZS System Calibration
1, 0
ZS calibration on AIN at selected gain
3 × 1/output rate
4 × 1/output rate + tP
FS System Calibration
1, 1
FS calibration on AIN at selected gain
3 × 1/output rate
4 × 1/output rate + tP


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