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AD7707 Datasheet(PDF) 35 Page - Analog Devices

Part # AD7707
Description  3-Channel 16-Bit, Sigma-Delta ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7707 Datasheet(HTML) 35 Page - Analog Devices

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Rev. B | Page 35 of 52
The AD7707 operates with power supplies between 2.7 V and
5.25 V. There is no specific power supply sequence required for
the AD7707, either the AVDD or the DVDD supply can come up
first. In normal operation, the DVDD must not exceed AVDD by
0.3 V.
the latch-up performance of the AD7707 is good,
is important that power is applied to the AD7707 before signals
at REF IN, AIN, or the logic input pins to avoid excessive currents.
If this is not possible, the current that flows in any of these pins
should be limited to less than 100 mA. If separate supplies are
used for the AD7707 and the system digital circuitry, the AD7707
should be powered up first. If it is not possible to guarantee this,
current limiting resistors should be placed in series with the
logic inputs to again limit the current. Latch-up current is
greater than 100 mA.
TA = 25°C
GAIN = 128
fCLK = 2.4576MHz
fCLK = 1MHz
Figure 19. IDD vs. Supply Voltage
The current consumption on the AD7707 is specified for supplies
in the range 2.7 V to 3.3 V and in the range 4.75 V to 5.25 V. The
part operates over a 2.7 V to 5.25 V supply range and the IDD for
the part varies as the supply voltage varies over this range. There is
an internal current boost bit on the AD7707 that is set internally
in accordance with the operating conditions. This affects the
current drawn by the analog circuitry within these devices.
Minimum power consumption is achieved when the AD7707 is
operated with an fCLKIN of 1 MHz or at gains of 1 to 4 with fCLKIN
= 2.4575 MHz as the internal boost bit is off reducing the analog
current consumption. Figure 19 shows the variation of the
typical IDD with VDD voltage for both a 1 MHz crystal oscillator
and a 2.4576 MHz crystal oscillator at 25°C. The AD7707 is
operated in unbuffered mode. The relationship shows that the
IDD is minimized by operating the part with lower AVDD/DVDD
voltages. AIDD/DIDD on the AD7707 is also minimized by using an
external master clock or by optimizing external components
when using the on-chip oscillator circuit.
Because the analog inputs and reference input are differential,
most of the voltages in the analog modulator are common-
mode voltages. The excellent common-mode rejection of the
part removes common-mode noise on these inputs. The digital
filter provides rejection of broadband noise on the power
supplies, except at integer multiples of the modulator sampling
frequency. The digital filter also removes noise from the analog
and reference inputs provided
those noise sources do not
saturate the analog modulator. As a result, the AD7707 is more
immune to noise interference than a conventional high
resolution converter. However, because the resolution of the
AD7707 is so high, and the noise levels from the AD7707 so
low, care must be taken with regard to grounding and layout.
The printed circuit board that houses the AD7707 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes, which can be separated easily. A
minimum etch technique is generally best for ground planes
because it gives the best shielding. Digital and analog ground
planes should only be joined in one place to avoid ground
loops. If the AD7707 is in a system where multiple devices
require AGND-to-DGND connections, the connection should
be made at one point only, a star ground point, which should be
established as close as possible to the AD7707.
Avoid running digital lines under the device because these may
couple noise onto the analog circuitry within the AD7707. The
analog ground plane should be allowed to run under the AD7707
to reduce noise coupling. The power supply lines to the AD7707
should use wide traces to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals like clocks should be shielded with digital ground to
avoid radiating noise to other sections of the board and clock
signals should never be run near the analog inputs. Avoid crossover
of digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects
of feedthrough through the board. A microstrip technique is by far
the best, but is not always possible with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes while signals are placed on the solder side.
Good decoupling is important when using high resolution ADCs.
All analog supplies should be decoupled with a 10 μF tantalum
capacitor in parallel with 0.1 μF ceramic capacitors to AGND.
To achieve the best performance from these decoupling
components, they must be placed as close as possible to the
device, ideally right up against the device. All logic chips should
be decoupled with 0.1 μF disc ceramic capacitors to DGND.

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