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AD7674 Datasheet(PDF) 22 Page - Analog Devices |
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AD7674 Datasheet(HTML) 22 Page - Analog Devices |
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22 / 28 page 
AD7674 Rev. A | Page 22 of 28 In Read after Conversion mode, it should be noted that unlike in other modes, the BUSY signal returns low after the 18 data bits are pulsed out and not at the end of the conversion phase, which results in a longer BUSY width. To accommodate slow digital hosts, the serial clock can be slowed down by using DIVSCLK. t3 BUSY CS, RD CNVST SYNC SCLK SDOUT 12 3 16 17 18 D17 D16 D2 D1 D0 X EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 t14 t20 t15 t16 t22 t23 t29 t28 t18 t19 t21 t30 t25 t24 t26 t27 03083-0-040 Figure 40. Master Serial Data Timing for Reading (Read after Convert) RDC/SDIN = 1 INVSCLK = INVSYNC = 0 D17 D16 D2 D1 D0 X 12 3 16 17 18 BUSY SYNC SCLK SDOUT CS, RD CNVST t3 t1 t17 t14 t15 t19 t20 t21 t16 t22 t23 t24 t27 t26 t25 t18 EXT/INT = 0 03083-0-046 Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) SLAVE SERIAL INTERFACE External Clock The AD7674 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both low, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or a discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 42 and Figure 43 show the detailed timing diagrams of these methods. While the AD7674 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or |
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