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AD7674 Datasheet(PDF) 20 Page - Analog Devices
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AD7674 Datasheet(HTML) 20 Page - Analog Devices
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Rev. A | Page 20 of 28
Figure 32. PSRR vs. Frequency
POWER DISSIPATION VERSUS THROUGHPUT
In Impulse mode, the AD7674 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which
allows for a significant power savings when the conversion rate
is reduced, as shown in Figure 33. This feature makes the
AD7674 ideal for very low power battery applications. It should
be noted that the digital interface remains active even during
the acquisition phase. To reduce the operating digital supply
currents even further, the digital inputs need to be driven close
to the power rails (DVDD and DGND), and OVDD should not
exceed DVDD by more than 0.3 V.
SAMPLING RATE (SPS)
Figure 33. Power Dissipation vs. Sample Rate
Figure 34 shows the detailed timing diagrams of the conversion
process. The AD7674 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by PD, until the conversion is complete. The
CNVST signal operates independently of CS and RD signals.
Figure 34. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This may be achieved by using a dedicated
oscillator for CNVST generation, or to clock it with a high
frequency low jitter clock, as shown in Figure 27.
In Impulse mode, conversions can be initiated automatically. If
CNVST is held low when BUSY goes low, the AD7674 controls
the acquisition phase and automatically initiates a new
conversion. By keeping CNVST low, the AD7674 keeps the
conversion process running by itself. Note that the analog input
has to be settled when BUSY goes low. Also, at power-up,
CNVST should be brought low once to initiate the conversion
process. In this mode, the AD7674 could sometimes run
slightly faster than the guaranteed limits of 570 kSPS in Impulse
mode. This feature does not exist in Warp or Normal modes.
The AD7674 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7674 digital interface also accommodates both 3 V and 5 V
logic by simply connecting the AD7674’s OVDD supply pin to
the host system interface digital supply. Finally, by using the
OB/2C input pin in any mode but 18-bit interface mode, both
twos complement and straight binary coding can be used.
The two signals, CS and RD, control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7674 in
multicircuit applications, and is held low in a single AD7674
design. RD is generally used to enable the conversion result on
the data bus.
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