Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com

SP3249E_100_013111

7

DESCRIPTION

The SP3249E device meets the EIA/TIA-232

and ITU-T V.28/V.24 communication protocols

and can be implemented in battery-powered,

portable, or hand-held applications such as

notebook or palmtop computers. The SP3249E

devices feature Exar's proprietary and patented

(U.S.-- 5,306,954) on-board charge pump cir-

cuitrythatgenerates±5.5VRS-232voltagelevels

from a single +3.0V to +5.5V power supply. The

SP3249E devices can guarantee a data rate of

250kbps fully loaded.

TheSP3249Eisa5-driver/3-receiverdevice,ideal

for portable or hand-held applications.

THEORY OF OPERATION

The SP3249E device is made up of three basic

circuit blocks:

1. Drivers

2. Receivers

3. The Exar proprietary charge pump

Drivers

The drivers are inverting level transmitters that

convert TTL or CMOS logic levels to 5.0V EIA/

TIA-232 levels with an inverted sense relative

to the input logic levels. Typically, the RS-232

output voltage swing is +5.4V with no load and

+5V minimum fully loaded. The driver outputs are

protected against infinite short-circuits to ground

without degradation in reliability. These drivers

comply with the EIA-TIA-232-F and all previous

RS-232 versions.

The drivers can guarantee a data rate of 250kbps

fully loaded with 3kΩ in parallel with 1000pF,

ensuring compatibility with PC-to-PC communi-

cation software. All unused drivers inputs should

be connected to GND or V

The slew rate of the driver output is internally

limited to a maximum of 30V/µs in order to meet

theEIAstandards(EIARS-232D2.1.7,Paragraph

5). The transition of the loaded output from HIGH

toLOWalsomeetsthemonotonicityrequirements

of the standard.

Figure 7 shows a loopback test circuit used to

test the RS-232 drivers. Figure 8 shows the test

results of the loopback circuit with all five drivers

active at 120kbps with typical RS-232 loads in

parallel with 1000pF capacitors. Figure 9 shows

the test results where one driver was active

at 250kbps and all five drivers loaded with an

RS-232 receiver in parallel with a 1000pF ca-

pacitor. A solid RS-232 data transmission rate

of 120kbps provides compatibility with many

designs in personal computer peripherals and

LAN applications.

Receivers

The receivers convert +5.0V EIA/TIA-232

levels to TTL or CMOS logic output levels.

Since receiver input is usually from a transmis-

sion line where long cable lengths and system

interference can degrade the signal, the inputs

have a typical hysteresis margin of 300mV. This

ensures that the receiver is virtually immune to

noisy transmission lines. Should an input be left

unconnected, an internal 5kΩ pulldown resistor

to ground will commit the output of the receiver

to a HIGH state.

Figure 6. Interface Circuitry Controlled by

Microprocessor Supervisory Circuit

SP3249E

24

21

3

1

23

4

22

GND

C1+

C1-

C2+

C2-

V+

V-

0.1µF

+

C2

C5

C1

+

+

C3

C4

+

+

2

5kΩ

5kΩ

5kΩ

20

19

18

17

16

14

5

6

7

8

9

11

RS-232

OUTPUTS

RS-232

INPUTS

UART

or

Serial µC

TxD

RTS

DTR

RxD

CTS

DSR

DCD

RI

15

13

10

12

0.1µF

0.1µF

0.1µF

0.1µF